IEEE Solid-States Circuits Magazine - Fall 2023 - 63

cable connections, and ESD coupling
between different IC components and
subsystems. For ICs with pins connected
to external interfaces, the IC
designer must identify the impact
on the IC, determine whether the IC
needs to withstand a higher voltage or
some residual ESD stress, and translate
the information to a stress waveform
at the pin of the IC. The concepts
of primary and secondary protection
are described in Figure 5. This is a codesign
activity as the system knowledge
is required to define a relevant
IC design specification. The " SystemEfficient
ESD Design (SEED) " concept
provides a framework for the IC designer
and system designer to work
together with the relevant information
from the IC passed to the system [14].
In this framework, the " ESD window "
concept is extended to the system,
enabling the selection of the primary
clamp [transient voltage suppressor
(TVS) or other passive devices] with a
clamping voltage that will protect the
sensitive ICs from external ESD while
maintaining signal integrity. As the
system can be powered up during this
stress, the residual ESD stress at the
pin and the ESD design window must
be assessed in every operating mode.
The impact of the decoupling capacitors
and the trace impedance on the
residual pulse means that every system
may have a unique response.
Looking to the Future
The ability to scale semiconductor
electronics reliably, mitigating the
ubiquitous threat of ESD, continues
to build on the early pioneering
work in three key domains of ESD
controls: ESD models and ESD protection
concepts and solutions. (See
Table 3 for a comparison.)
Technology scaling, the introduction
of new materials, and the heterogeneous
integration required to meet
the demands in the communication,
automotive, and computer industries
will continue to challenge ESD robust
IC and system design in the years to
come. Some of the critical areas of
research are outlined in the Electrostatic
Discharge Association (ESDA)
WP3 " ESD and Latch-up Challenges:
An Outlook Until 2030 " [15], including
references to the new device architectures
and performance targets
that can impact ESD and latch-up protection
design. Industry leaders predict
that more stringent ESD controls
will be needed to enable the lowering
of HBM and CDM targets within the
ESD-controlled area, driven by highspeed
die-to-Die interfaces of 2.5D
and 3D integrated products. At the
same time, the ESD exposure in the
end-user environment will not scale.
These are some of the engineering
challenges and opportunities ahead.
References
[1] E. R. Freeman and J. R. Beall, " Control of
electrostatic discharge damage to semiconductors, "
in Proc. 12th Int. Rel. Phys.
Symp., Las Vegas, NV, USA, 1974, pp. 304-
312, doi: 10.1109/IRPS.1974.362663.
[2] Protection of Electrical and Electronic
Parts, Assemblies and Equipment (Excluding
Electrically Initiated Explosive Devices), "
ANSI/ESD S20.20-2021, 2021.
[3] " White paper 1: A case for lowering component
level HBM/MM ESD specifications
and requirements, " Industry Council on
ESD Target Levels, Dallas, TX, USA, Jun.
2018. [Online]. Available: https://www.
esdindustrycouncil.org/ic/en/documents/
whi te-paper -1-a- case - for -lower ingcomponent-level-hbm-mm-esd
[4]
" White paper 2: A case for lowering component
level CDM ESD specifications and
requirements - May 2021, Rev 3.0, " Industry
Council on ESD Target Levels, Dallas,
TX, USA, May 2021.
https://www.esdindustrycouncil.org/ic/
en/documents/white-paper-2-a-case-forlowering-component-level-cdm-esd-sp
[5]
M. Johnson, R. Ashton, and S. Ward,
" FCDM measurements of small devices, "
in Proc. 31st EOS/ESD Symp., Anaheim,
CA, USA, 2009, pp. 1-8.
[6] C. Duvvury and A. Amerasekera, " ESD: A
pervasive reliability concern for IC technologies, "
Proc. IEEE, vol. 81, no. 5, pp.
690-702, May 1993, doi: 10.1109/5.220901.
[7] A. Dong, J. Xiong, S. Mitra, W. Liang, R.
Gauthier, and A. Loiseau, " Comprehensive
study of ESD design window scaling
down to 7nm technology node, " in
Proc. 40th Elect. Overstress/Electrostatic
Discharge Symp. (EOS/ESD), Reno, NV,
USA, 2018, pp. 1-8, doi: 10.23919/EOS/
ESD.2018.8509689.
[8] J. Liu, N. Carels, and N. Peachey, " Characterization
and analysis of RF switches
in SOI technology for ESD protection, " in
Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Dallas,
TX, USA, 2022, pp. P13-1-P13-5, doi:
10.1109/IRPS48227.2022.9764421.
[9] D. Kontos, I. King, W. Chen, and V. Vashchenko,
" Circuit level
implementation
of ESD self protected LDMOS open drain
output, " in Proc. 44th Annu. EOS/ESD
Symp. (EOS/ESD), Reno, NV, USA, 2022,
pp. 1-7, doi: 10.23919/EOS/ESD54763.
2022.9928525.
[10] S. Kim et al., " A new ESD self-protection structure
for 700V high side gate drive IC, " in Proc.
29th Int. Symp. Power Semicond. Devices IC's
(ISPSD), Sapporo, Japan, 2017, pp. 467-470,
doi: 10.23919/ISPSD.2017.7988880.
[11] Electromagnetic Compatibility (EMC) -
Part 4-2: Testing and Measurement Techniques
- Electrostatic Discharge Immunity
Test, IEC 61000-4-2 Ed 2.0, IEC, Geneva,
Switzerland, Dec. 2008.
[12] Road Vehicles - Test Methods for Electrical
Disturbances from Electrostatic Discharge,
ISO 10605:2008, International Organization
for Standardization, Geneva,
Switzerland, 2008.
[Online]. Available:
https://www.iso.org/standard/41937.html
[13] For Electrostatic Discharge Sensitivity Testing
Human Body Model (HBM) - Component
Level, ANSI/ESDA/JEDEC JS-001-2010, 2010.
[14] C. Duvvury and H. Gossner, System Level
ESD Co-design. New York, NY, USA: WileyIEEE
Press, 2015.
[15] " White paper - ESD and latch-up challenges
- An outlook until 2030, " EOS/ESD
Association, Inc., Rome, NY, USA, 2023.
[Online]. Available:
About the Author
Ann Concannon (ann.concannon@
ti.com) received her B.E. degree in
electronic engineering from NUIG,
Ireland, in 1991, and she received her
Ph.D. degree from University College
Cork, Ireland, in 1996 for her work
on device simulation of floating gate
nonvolatile memory. She is a distinguished
member of the technical
staff at Texas Instruments, working
in the Analog ESD Group, Dallas, TX
75266-0199 USA, working with technology
development teams, design
teams, and external customers to
engage early on ESD challenges on
projects with high visibility on execution
and revenue opportunities.
Awarded a Marie Curie Fellowship in
1996, she worked on joint Si device
development projects with European
industry and led a research group at
the Tyndall Institute in Ireland. She
moved to Santa Clara, CA, USA, after
joining National Semiconductor
in 2000, and subsequently, to Texas
Instruments in 2011, where she has
focused on ESD, electrical overstress,
and latch-up. She is an active member
of the Electrostatic Discharge Association
(ESDA), with many publications
and patents in NVM, Si, and ESD. In
2017, she was elected to the board
of the ESDA, and she is a founding
member of the Bay Area ESD group; a
member of the ESDA education committee;
the general chair of the 45th
Annual EOS/ESD symposium in Riverside,
CA, USA, in October 2023. She
is a Senior Member of IEEE.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
63

https://www.iso.org/standard/41937.html https://www.esdindustrycouncil.org/ic/en/documents/white-paper-1-a-case-for-lowering-component-level-hbm-mm-esd https://www.esdindustrycouncil.org/ic/en/documents/white-paper-1-a-case-for-lowering-component-level-hbm-mm-esd https://www.esdindustrycouncil.org/ic/en/documents/white-paper-1-a-case-for-lowering-component-level-hbm-mm-esd https://www.esdindustrycouncil.org/ic/en/documents/white-paper-1-a-case-for-lowering-component-level-hbm-mm-esd https://www.esdindustrycouncil.org/ic/en/documents/white-paper-2-a-case-for-lowering-component-level-cdm-esd-sp https://www.esdindustrycouncil.org/ic/en/documents/white-paper-2-a-case-for-lowering-component-level-cdm-esd-sp https://www.esdindustrycouncil.org/ic/en/documents/white-paper-2-a-case-for-lowering-component-level-cdm-esd-sp http://dx.doi.org/10.1109/5.220901

IEEE Solid-States Circuits Magazine - Fall 2023

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