IEEE Solid-States Circuits Magazine - Fall 2023 - 72

Finally, Staszewski shared his recent
captivating work on quantum computers
on a CMOS chip. He started the talk
by exploring emerging approaches
and challenges in the implementation
of quantum computers using CMOS
technologies. Then, he provided a
future perspective of the field toward
the realization of a quantum computer
system-on-chip. Staszewski concluded
his presentation with a recent
advancement in the realization of a
quantum computer.
The SSCS and CASS Thailand
Chapter would like to extend their
sincere appreciation to Kasetsart
University, King Mongkut's Institute
of Technology Ladkrabang, and
Silicon Craft Technology PLC for
co-organizing the event. We would
also like to extend a special thanks
to the speakers Staszewski and
Teerachot, who delivered extremely
engaging talks.
-Kriangkrai Sooksood ,
IEEE Thailand SSCS Chapter Chair
O
SSCS Kansai Chapter Technical Seminar, Special Reports
on 2023 Symposium on VLSI Technology and Circuits
On 25 July 2023, we organized a
technical seminar presenting special
reports from the 2023 Symposium
on VLSI Technology and Circuits.
The seminar focused on circuit technology,
and the invited speakers
presented their latest research findings
(Figure 1).
The Circuits Session consisted
of 15 presentations, while the Technology/Circuits
Joint Focus Session
included six presentations. Here, we
introduce only the presentations of
the Circuits Session. J. Suzuki from
the Tokyo Institute of Technology
delivered a presentation on a lowDigital
Object Identifier 10.1109/MSSC.2023.3309470
Date of current version: 14 November 2023
power-consumption deep neural network
(DNN) accelerator. R. Sumikawa
from the University of Tokyo discussed
a DNN processor for a 35 voice
commands recognition application.
Prof. S. Dosho from the Tokyo Institute
of Technology introduced a lowpower
direct-conversion frequency
analyzer. Dr. T. Oshima from Hitachi
presented on the topic of 7-nm CMOS
cyclic ADC. Y. Komura from the Semiconductor
Energy Laboratory discussed
2D arranged display drivers
achieved by an OS/Si structure. Y.
Aoyagi from TSMC Design Technology
Japan presented a talk on a 3-nm
27.6-Mb/mm2
self-timed SRAM. Y.
Osada from TSMC Design Technology
Japan presented a 3.7-GHz multibank
high-current single-port cache SRAM.
K. Suzuki from Sony Semiconductor
Solutions talked about a 40-nm 2-kb
MTJ-based nonvolatile SRAM. K. Shiraishi
from KIOXIA presented a 1-TB
3 b/cell 3D flash memory of more
than 17-GB/mm2
bit density. Dr. H.
Luong from Sony Semiconductor
Solutions presented a gain-adaptive
single-slope column ADC. T. Takatsuka
from Sony Semiconductor Solu -
tions gave a talk on a 3.36-μm-pitch
SPAD photon-counting image sensor.
Dr. Z. Yang from the University of
Tokyo presented a reference-sampling
PLL with a low-ripple double-sampling
PD. Dr. M. Fukazawa from Renesas
Electronics presented on the topic
of a 24 OSR to simplify an antialiasing
FIGURE 1: Lecturers, attendees of the lecture, and SSCS Kansai and Japan Chapter officers.
72
FALL 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE

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IEEE Solid-States Circuits Magazine - Fall 2023

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