IEEE Solid-States Circuits Magazine - Fall 2023 - 89

Era of Hardware: AI-Driven, Software-Defined,
and Uncomfortably
Exciting. " Computing demand accelerated
by the AI revolution, cloud,
and smart edge coupled with the
slowdown of Moore's law are challenging
traditional assumptions on
how to achieve cheaper and more
energy-efficient computing. He discussed
how to rethink the design
of efficient future hardware using
custom silicon accelerators and efficient
hardware utilization through
software-defined systems design. In
his talk, " Quantum Computing From
Hype to Game Changer, " Hiroyuki
Mizuno from Hitachi explored the
use of existing IC technologies as a
stopgap to realize the next milestone
to develop silicon quantum computers-qubit
operation in a scalable
qubit array structure. Finally, in
" Searching for Nonlinearity: Scaling
Limits in NAND Flash, " Siva Sivaram
from Western Digital explored the
use of wafer bonding technology to
decouple the memory array from
complex logic circuits, allowing new
high-speed logic integration with the
memory layers and reducing manufacturing
cycle times. Moreover, this
technology enables the industry to
move away from a one-size-fits-all
NAND die to customized solutions
for various applications and systemlevel
savings. (See Figure 2.)
Workshops, Short Courses,
and Forum
To warm up the symposium attendees,
Sunday evening hosted six parallel
workshop sessions to packed
audiences. The technology workshops
covered EUV lithography and beyond,
increasing wafer backside functionality
beyond just power delivery, and
materials to system co-optimization
methodology for quickly evaluating
the feasibility of development
in advanced technology nodes. The
circuits workshops focused on the
need for uniform and rigorous benchmarking
of machine learning ICs and
systems, 3D image sensors, and open
source process design kits and electronic
design automation toward the
democratization of chip design.
The Symposium Short Course was
a sold-out affair and featured two
parallel full-day tracks on Monday. A
perennial crowd favorite, the Technology
Short Course, covered " Advanced
CMOS Technologies for 1 nm and
Beyond " including novel logic technologies
and associated front- and
back-end-of-line processes, EUV
lithography, transistor evolution from
silicon to novel 2D materials (such as
transition metal dichalcogenides), 3D
integration from a backside power distribution
network and heterogeneous
integration as well as future metrology
for production. The Circuits Short
Course focused on " Future Directions
in High-Speed Wireline and Optical
IO, " with industry experts delving
into the latest advances in SerDes system
design, coherent ASICs, silicon
photonics, state-of-the-art chipletbased
connectivity, innovative packaging,
high-speed transceivers, and
memory interfaces.
The symposium concluded on Friday
with a full-day forum on " Compute
Paradigms for Secured Microelectronics
and Combinatorial Optimization. "
The vision of the VLSI Forum is to
extend the scope of the symposium
with experts proposing future directions
and showcasing cutting-edge
applications of VLSI. This year's forum
included content on hardware security,
cryptographic circuit technology,
cybersecurity as well as combinatorial
optimization accelerators based
on processors, FPGA, and a superconducting
quantum annealer.
Demo Session
The well-attended demonstration session
(Figure 3) was held on Monday
evening, providing participants an
opportunity for lively in-depth interactions
with authors of selected
papers from both Technology and
Circuits sessions. Decided by participant
voting, this year's Best Demo
Paper Awards were presented to K.
Han et al. from the National University
of Singapore for " A Novel Bridge
Transmission Line Method for ThinFilm
Semiconductors: Modeling, Simulation
Verification, and Experimental
Demonstration " and to C. Okada et al.
of Sony Semiconductor Solutions and
Sony Semiconductor Manufacturing
for " 216-fps 672 × 512 Pixel 3-μm Indirect
Time-of-Flight Image Sensor With
1-Frame Depth Acquisition for Motion
Artifact Suppression. "
Joint Technology/Circuit Highlights
Backside power delivery was arguably
this year's symposium topic that drew
the most enthusiasm. Intel presented
two companion papers to report a
high-yielding backside power delivery
technology, PowerVia Technology, to
extend Moore's law scaling (Figure 4).
(a)
(b)
(c)
(d)
FIGURE 2: Plenary speakers. (a) Surya Bhattacharya, (b) Partha Ranganathan, (c) Hiroyuki Mizuno, and (d) Siva Sivaram.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
89

IEEE Solid-States Circuits Magazine - Fall 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2023