IEEE Solid-States Circuits Magazine - Fall 2023 - 9

The nonlinear dependence of i
upon m causes larger increments if
m is near 8 and smaller ones if m
is near zero or 16. Figure 9 displays
this behavior.
Phase Correction by Predistortion
Equation (3) and Figure 9 give us an
idea: the interpolating inverters near
the midscale can be made weaker so
as to obtain more uniform phase
increments. Alternatively, those at
the top and bottom of the array in
Figure 8(a) can be made stronger,
a more practical remedy in view
of the small widths that we have
chosen. We say the array is predistorted.
But with the series resistors
present, we benefit from additional
flexibility here:
R R-116 permit predistortion
and obviate the need for
nonuniform inverters.
Resistor predistortion must be carried
out while bearing in mind the
resistance " spread, " i.e., the maximumto-minimum
ratio, that it requires. We
assume a 500-X unit resistor and set
an upper bound of 3k .X
To increase the increments near
m 0= and m ,16= we select R1
2 = == X Similarly, to
=
R RR .500
15
16
decrease the phase steps in the vicinity
of
m ,8= we have RRR
13
14
R 2k12
= X
Figure 10 plots the results, revealing
minimum and maximum steps
equal to 420 fs and 636 fs, respectively.
Predistortion has improved
the linearity but we still do not meet
our 400-fs resolution target.
Raising the Resolution
We wish to raise the PI resolution
by a factor of 2. Rather than double
the number of inverter/resistor
branches-which would double
the input capacitance-we surmise
that a fine increment can be created
by adding a " half-strength "
branch. Illustrated in Figure 11(a),
such a branch consists of Inv0
and
R0 and contributes a step equal to
0.5 least-significant bit (LSB). Inv0
employs transistors whose lengths
are doubled by series stacking.
WP = 300 nm
WN = 200 nm
FIGURE 11: Addition of a 0.5-LSB branch to double the resolution.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
9
FIGURE 10: The output waveforms after predistortion.
WP = 300 nm
WN = 200 nm
VI or VQ
Inv1
R1
RF = 3 kΩ
X
Inv16
R16
WP = 8 µm
WN = 4 µm
Vout
VDD
Inv0
R0
78 9
R 3k10 = X Finally, we opt for RR
RR 1k== X and RRR
===
==
34
56 11== =
66
68
70
72
Time (ps)
74
76
78
The choice of R ,0 however, entails
a compromise in view of predistortion.
If R0
is twice R ,1
and m ,16=
then the
0.5-LSB branch yields a proper step
near m 0=
m .8= For this reason, we choose
,
but an excessively
large increment in the vicinity
of
R 2k0 = X arriving at the waveforms
shown in Figure 12. The phase steps
range from 156 fs to 362 fs.
10
20
30
40
50
60
70
80
90
51015
m
FIGURE 9: The output phase versus the
input thermometer code.
1,000
200
400
600
800
Four-Quadrant PI
It is desirable for the PI output to
rotate, seamlessly, from 0° to 360°
[Figure 13(a)]. This requires that the
circuit interpolate between VI
V ,Q VQ and ,VI etc. We then modify
the design as shown in Figure 13(b),
where another rank of MUXes is
inserted to select VI
or VI and VQ
necessary for this operation.
The 2-to-1 MUXes in Figure 13(b)
are realized by transmission gates
[Figure 13(c)] The cascaded switches
raise the input capacitance by about
a factor of 4, presenting a total load
of roughly (. )( )
16 fF to VI and to VQ for operation
05 48 1mfF## #
n
=
in the first quadrant. Two inverters
driving these loads would draw
about 0.9 mW at 28 GHz. The cascaded
transistors also attenuate the
input by about 15%.
or
V .Q Two additional control bits are
and
Phase (°)
Voltage (mV)
IEEE Solid-States Circuits Magazine - Fall 2023

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