IEEE Solid-States Circuits Magazine - Fall 2023 - 90

Moving supply connections to the
backside enabled standard cell utilization
to exceed 90% in large areas of
the core while showing more than 5%
frequency benefit in silicon because
of the 30% reduced IR droop.
In the area of devices and accelerators
for machine learning, Macronix
demonstrated a high-density
(43 Gb) in-memory search chip based
on a 96-layer 3D NAND product.
The novel String-Select Line design
achieved 300 Gb/s search bandwidth
with a measured power of less than
400 mW, accelerating both exact
TCAM and proximity Hamming-distance
searches.
Chiplets continue to gain momentum
FIGURE 3: Participants and authors engaged in lively demonstrations showcasing device
characterization, chip operation, and potential applications for circuit-level innovations.
with demonstrations of inc reasingly
complex heterogeneous integration of
compute cores, memory, and required
on-package connectivity, such as that
published by AMD (Figure 5).
FIGURE 4: Intel PowerVia technology showing progression in backside power rail functionality.
Technology Highlights
The industry has been eagerly awaiting
the announcement of a production-ready
GAA stacked nanosheet
technology at a conference. This
year's symposium ended that wait
with Samsung reporting technical
details on the highly anticipated
transition from FinFET to the GAA
transistor architecture that Samsung
named a Multi-Bridge-Channel
FET (MBCFET). The world's first GAA
3-nm Foundry Platform Technology,
SF3, provides 22% speed and
34% power improvements and 0.79 ×
logic area reduction over the 4-nm
FinFET platform (Figure 6).
Researchers at imec reported on
FIGURE 5: State-of-the-art AMD product enabled by advanced packaging technology.
silicon nanosheet monolithic complementary
FETs (CFETs), i.e., NMOS and
PMOS transistors stacked on top of
one another, at an industry-relevant
gate pitch of 48 nm with source/
drain and contacts formed for either
top or bottom devices. Functional
devices with excellent subthreshold
swing (SSSAT
= 70-75 mV/decade) were
reported for top and bottom devices
being both NMOS and PMOS (Figure 7).
In the area of memory technol(a)
(b)
FIGURE
6: (a) Performance/power/area comparison between the previous 4-nm FinFET
(SF4) and the world's first 3-nm SF3 GAA. (b) Cross section of MBCFET highlighting process
optimization.
90
FALL 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
ogy, several key advances in 3D flash
memory manufacturing were introduced.
The formation of tall vertical
vias is a key enabler to extend the
stacking of even more layers. Kioxia
and Western Digital demonstrated
metal-induced lateral crystallization
techniques for fabricating more than
300 layers by creating 14-μm-long

IEEE Solid-States Circuits Magazine - Fall 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2023

Contents
IEEE Solid-States Circuits Magazine - Fall 2023 - Cover1
IEEE Solid-States Circuits Magazine - Fall 2023 - Cover2
IEEE Solid-States Circuits Magazine - Fall 2023 - Contents
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IEEE Solid-States Circuits Magazine - Fall 2023 - Cover3
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