IEEE Solid-States Circuits Magazine - Fall 2023 - 91

macaroni silicon channels in the
vertical memory holes. Authors at
Tokyo Electron Miyagi developed
a novel environmentally friendly
carbonless etch process for high
aspect hole patterning using cryogenic
temperature devices. Also,
SK Hynix presented programmable
3D ferroelectric NAND quad-level
cell operation using their 3D charge
trap nitride NAND test vehicle. They
optimized their cell stack structure
to achieve triple- and quadruplelevel
cell operation with respective
minimum Vth
gap margins of 0.45 V
and 0.24 V between adjacent states.
In the continuous drive to further
shrink image sensor pixels, Sony
proposed for the first time a twolayer
transistor pixel stacked CMOS
image sensor with 2-fin undoped
pixel-fin FETs. Thanks to the undoped
channel and wider channel FinFET
width, they report a 2.42 × transconductance
improvement, 15% random
noise, and 99.3% random telegraph
signal reduction.
Circuits Highlights
In the processor space, researchers
at MediaTek announced a digital
compute-in-memory (DCIM) macro to
enable an ultra-low power deep learning
system for end-to-end Always-onVision.
The prototype SoC comprised
a DCIM-based deep learning accelerator,
RISC-V microprocessor, and interface
to an off-chip image sensor.
It
supported mixed-precision computation
to balance power consumption
and desired accuracy, achieving
57 TOPS/W energy efficiency and
85.7% accuracy with mixed precision
for human detection on MobileNetV1.
The University of Michigan and
Intel reported a heterogeneous SiP
integrating a 14-nm FPGA chiplet
with two 22-nm DSP chiplets through
embedded multidie interconnect
bridges. The chiplets communicate
via Advanced Interface Bus (AIB)
1.0 and 2.0 interfaces. The SiP demonstrates
the first-ever AIB 2.0 I/O
prototype using 36-μm-pitch microbumps,
achieving 4 Gb/s/pin at
0.1 pJ/b. The SiP is programmable,
supporting a variety of workloads
and providing a peak performance
of 4.14 TFLOPS (FP16, half-precision
floating-point). A compilation flow is
developed to map workloads across
the FPGA and DSPs to optimize performance
and utilization.
In another demonstration of heterogeneous
integration, Intel proposed
integrating a silicon photonic
microring-based DWDM receiver
(Figure 8). A dither-based thermal
control unit tunes the microring
resonators in the optical demux to
align to the laser grid with subpicometer
resolution. The transceiver was
implemented as a 28-nm CMOS electric
IC stacked on a silicon photonic
IC, achieving a BER below 10−12
at
256 Gb/s, 3.6-dBm optical power,
and 3.8-pJ/b energy efficiency with
eight wavelengths uniformly spaced
apart by 200 GHz.
The memory domain witnessed
TSMC presenting a highly energyefficient
SRAM cache in a 3-nm FinFET
CMOS compatible with the wide supply
voltage operation mandated by DVFS.
Far-end bitline precharge and weakbit
mented
to overcome increased wiring
resistance and transistor voltagedependent
sensitivity in such advanced
nodes. A 3-nm test chip demonstrated
a high density of 27.6 Mb/mm2
FIGURE 7: Advanced CFET integration presented by imec.
tracking circuitries were impleand
operation
of 550 MHz to 2.8 GHz
across a wide voltage supply range
FIGURE 8: Heterogeneously integrated DWDM transceiver with electric IC and photonic IC.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2023
91
IEEE Solid-States Circuits Magazine - Fall 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2023
