IEEE Solid-States Circuits Magazine - Fall 2023 - 92

of 0.48 to 1.2 V to achieve the best
FOM (density # Fmax
/VDD) reported
to date. For nonvolatile memory,
Kioxia reported more than 210 wordline
layers in a 1-Tb 3b/cell 3D flash
memory with bit density exceeding
17 Gb/mm2
. The memory employed
an eight-plane architecture to achieve
a low read latency of 40 ms and a
high programming throughput of
205 MB/s, a high interface speed of
3.2 Gb/s, hybrid row address decoders
to mitigate wiring congestion, and
a one-pulse-two-strobe technique to
reduce the sensing time by 18%.
In the area of image sensors, Sony
Semiconductor Solutions published
SPAD pixels capable of very wide
dynamic range. SPAD pixels are inherently
very sensitive in extremely
dark situations but are prone to
saturation in bright situations (Figure
9). In this article, the reset of the
SPAD pixel is periodically controlled
to suppress the SPAD pixel reaction in
bright scenes, thereby reducing the
power consumption. The pixel size
has also been shrunk by reducing the
in-pixel counter bit to 8 bits, enabling
the world's smallest pixel size of
3.36 mm2
.
For advances in frequency synthesis,
an example was KAIST's low-jitter
clock multiplier producing 12.24 GHz.
The architecture employed a ringoscillator-type
multiplier to bring the
area down to 0.066 mm2
and a power
gating technique to achieve a higher
frequency output. A built-in calibration
circuit suppressed reference
spurs to below -60 dBc.
In the area of data converters,
FIGURE 9: SPAD pixel allows for extremely dark scenes to be captured while still allowing
bright scenes to be captured without saturation.
the University of Michigan proposed
a new hybrid ADC architecture that
uses a VCO-based continuous-time
delta-sigma modulator with a noiseshaping
(NS) SAR quantizer. An antialiasing
filter that bridges the VCO
front end with the NS SAR enables
time-domain information to be
directly sampled as voltage-domain
information. The 28-nm prototype
achieved a 84.2-dB SNDR and 86.8-dB
DR within a 1-MHz bandwidth while
consuming 1.62 mW at 100 MSample/s.
(See Figure 10).
One notable analog technique
FIGURE 10: A new hybrid ADC architecture with an antialiasing filter that bridges the VCO
front end with the NS SAR.
showcases the work of ETH Zurich
presenting a noise-efficient AFE for
low-power sensor systems. The proposed
AFE employed an LNA based
on series-parallel converters whose
input impedance is boosted to 389 MΩ
using an input-resistance boosting
loop and a capacitive positive feedback
loop. This impedance-boosting
technique provides 39 × improvement
compared to prior work. The
AFE achieved the lowest reported
noise and power efficiency factors of
0.34 and 0.1, respectively, while consuming
only 370 nW. (See Figure 11).
In the area of biomedical circuits,
FIGURE 11: Input impedance-boosted analog front end.
92
FALL 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
authors at the Southern University
of Science and Technology of China,
the National University of Singapore,
and the Singapore N.1 Institute for
Health developed a body area network
transceiver IC that provides
power and data communication to
each sensor node using a single
electrode for continuous monitoring
of health-care information with a
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