IEEE Solid-States Circuits Magazine - Spring 2020 - 11

HCTLE

VDD

An
Md
R1

M1

A0

Vout
f1

Vin

f

(a)

M2

(b)
VDD

M1

Cb

M2

VDD

X

Ca

M1
Y

Vout
Vin

M3

M4

CGD1
X

(c)

Ca

Y

(d)

FIGURE 14: CTLE application of active inductors: (a) the typical CTLE frequency response, (b)
the CTLE implementation using active inductors, (c) cancellation of gate-drain capacitance in
a differential topology, and (d) an illustration of the capacitors' role.

example [4] where a differential
pair delivers a large voltage swing
to a transmission line and the network comprising M 1-M 6 serves as a
tunable inductive load. We recognize that M 1 and M 2 play the same
role as M 1 in Figure 11 and M 5 and
M 6 the same role as R 1. Moreover,
source followers M 3 and M 4 act
as level shifters, allowing the gate
voltages of M 1 and M 2 to be lower
than their respective drain voltages
by VGS3, 4. This structure therefore
lends itself to low supply voltages.
The on-resistance of M 5 and M 6 can
be adjusted by means of their gate
voltage, thus providing a variable
boost factor [4].
Another interesting application
of active inductors is in continuoustime linear equalizers (CTLEs) used
in wireline receivers. A CTLE must

	

provide a high-pass response to partially compensate for the high-frequency loss of the channel through
which the data travels [Figure 14(a)].
We say the CTLE provides a "boost
factor," A n /A 0, and we make it programmable so as to accommodate
different channel losses.
We can envision the CTLE as a simple common-source stage and implement the responses in Figure 14(a) by
means of a variable load impedance;
specifically, since the slope of the
load must be programmable, we surmise that a variable inductance can
serve this purpose. The tunability
afforded by (12) thus proves useful
here, leading to the CTLE topology
shown in Figure 14(b) [5]. The inductance is tuned by varying the PMOS
load's transconductance. This device is decomposed into a number of

units, each of which can participate
in the active inductor environment.
But, to ensure a constant low-frequency gain, A 0, when some of these
units turn off, additional diode-connected transistors are turned on [5].
This approach must still deal with
the voltage headroom consumed by
the PMOS transistors.
Recall from Figure 10(c) that the
gate-drain capacitance of the core
transistor in an active inductor degrades the performance. This issue
can be resolved in a differential topology by adding compensating capacitors [Figure 14(c)] [5]. Here, C a and C b
are chosen equal to the PMOS gatedrain capacitances. As illustrated in
Figure 14(d), the gate voltage of M 1 is
now unaffected by C GD1 because this
capacitance and C a inject equal and
opposite amounts of charge.
Active inductors can also serve
in analog filter design. In fact, some
classic filters were based on "simulated inductors" [6], circuits that
used op-amps and capacitors to emulate an inductive behavior.

References

[1]	 B. Christensen, "Monolithic semiconductor circuit with energy storage junction
and feedback to active transistor to produce two terminal inductance," U.S. Patent 3 160 835, Dec. 8, 1964.
[2]	 E. Sackinger and W. Fischer, "A 3 GHz, 32
dB CMOS limiting amplifier for SONET OC48 receivers," in Proc. IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers,
Feb. 2000, pp. 158-159. doi: 10.1109/
ISSCC.2000.839730.
[3]	 J. Im et al., "A 112-Gb/s PAM4 long-reach
wireline transceiver using a 36-way timeinterleaved SAR ADC and inverter-based
RX analog front end in 7-nm FinFET," in
Proc. IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, Feb. 2020, pp.
116-117.
[4]	 Y.-S. Lee, S. Sheikhaei, and S. Mirabbasi,
"A 10 Gb/s active-inductor structure with
peaking control in 90-nm CMOS," in Proc.
Asian Solid-State Circuits Conf., Nov. 2008,
pp. 229-232. doi: 10.1109/ASSCC.2008.
4708770.
[5]	 P. A. Francese et al., "Continuous-time
li--near equalization with programmable
active-peaking transistor arrays in a
14-nm FinFET 2-mW/Gb/s 16-Gb/s 2-tap
speculative DFE receiver," in Proc. IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig.
Tech. Papers, Feb. 2015, pp. 186-187. doi:
10.1109/ISSCC.2015.7062988.
[6]	 A. Sedra and K. Smith, Microelectronic Circuits, 5th ed. London, Oxford Univ. Press,
2004.


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