IEEE Solid-States Circuits Magazine - Spring 2020 - 49

similar square wave signals slightly
shifted in time. Figure 4(a) compares a
five-tap ring oscillator made of inverters and oscillating at a frequency f0
with an equifunctional circuit as in
Figure 4(b), where an oscillator oscillating at 10f0 is connected to a fivetap ring counter: the outputs of both
circuits are exactly the same signals.
Therefore, the ring oscillator itself
suffices to implement the whole system in Figure 2 in a very compact and

Sampling
Clock

VCO
Output

f0, the SQNR is improved by 3 dB.
Therefore, the choice of the oscillator
and sampling frequencies enables the
optimization of the SQNR.
The typical VCO-based ADC circuit
used in practice differs from the conceptual circuit in Figure 2, although, in
the end, it performs the same function.
The difference lies in how the counter
is implemented. Most VCO-based ADCs
are implemented with a ring oscillator,
which is a circuit that produces many

y [n ]

an important design relation in VCObased ADCs: the resolution is proportional to the oscillator frequency
relative to the sampling frequency
(which corresponds to the number
of quantization bits in a traditional
amplitude-based ADC).
In addition, if the input signal is
oversampled beyond Nyquist, the
sampling period Ts is shorter, and
there will apparently be fewer counts
in the counter, resulting in a lower
resolution. However, the reality is
the opposite: the error introduced
by quantizing the frequency of the
oscillator into an integer number (the
count) is first-order noise-shaped: the
error obtained after and before sampling in the middle of a VCO cycle
always adds to one cycle. This fact is
illustrated in Figure 3, which shows
that the quantization error e[n] can be
written as the first-order difference
of a finite-power sequence. This firstorder noise shaping, in combination
with oversampling and digital decimation after the counter, improves
the signal-to-quantization-noise ratio
(SQNR) much more than if the oscillator frequency is increased.
The following approximate eq--
uation gives the ma ximum SQNR
of a VCO-based ADC with analog
signal bandwidth ABW, sampling
frequency fs, and oscillator rest
frequency f0 [32]:

Sampling
Edge

efinal [n-1] + einitial [n] = 1 → e [n] = einitial [n] + efinal [n] - 1 → e [n] = efinal [n] - efinal [n-1]
FIGURE 3: The signal behavior in the VCO-based ADC in Figure 2, with an illustration of the
noise shaping. The latter is due to the fact that the error efinal injected at the end of a counting cycle, combined with the error einitial at the beginning of the next counting cycle, always
adds up to 1 least significant bit.

SQNR [dB] .

fs
2f0
m.
m - 5.17 + 9 log 2 c
6 log 2 c
2ABW
fs

(1)
This equation shows that the SQNR
improves by 6 dB every time the
VCO frequency f0 is doubled relative
to the sampling frequency fs, as the
quantization resolution is increased
by one bit. If the oversampling ratio
is doubled as well as the quantization resolution, i.e., the sampling frequency fs is doubled together with
the oscillator frequency f0, the SQNR
improvement is 9 dB. An additional
consequence of this dependency is
that, if the sampling frequency fs is
doubled for a fixed oscillator frequency

f0
φ0

φ1

φ2

φ3

φ4

(a)
φ0

10f0

D Q

φ1

D Q

φ2

D Q

φ3

D Q

φ4

D Q

VCO
(b)
FIGURE 4: The comparison of (a) a ring oscillator and (b) an oscillator and counter.

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