IEEE Solid-States Circuits Magazine - Spring 2020 - 54

Practical Design Example
To illustrate the preceding concepts,
and as example of the different design
methodology needed for VCO-based
ADCs, we now describe the circuit given
in [9], which is intended for audio
applications. It is a very simple VCObased ADC, yet it shows the full potential of time encoding. The core of the
ADC consists of two twin VCOs implemented with 11-phase ring oscillators.
The VCOs are driven by a differential
transconductor that isolates them
from the input, which, in this case, is
a high-output-impedance microelectromechanical system microphone.
All current used by the transconductor is, at the same time, powering the
VCOs (see Figure 10). The transistors in
the ring oscillator have widths on the
order of 30 nm. This large transistor
size, compared to what would be used
for this frequency in a PLL, is needed
to satisfy the input-referred noise re--
quirement relative to the quantization
noise of the converter (on the order
of a few microvolts).
The chip uses the multiphase readout circuit in Figure 12 to count the
edges in the ring oscillator phases
W 1 ...W M with as little power as possible. The multiphase readout circuit
is implemented with a Gray counter
connected to a reference phase, providing a coarse quantization code
and an encoder block that refines the
total edge count from samples of the
ring oscillator state. The encoder
block operates at the sampling clock
(2.4  MHz in this case), much slower
than the coarse counter (approximately
50 MHz). The digital and analog power
consumption is each roughly half
the varchitecture pays off in distortion
mitigation (the peak SNDR is 70 dB in
20 kHz of bandwidth without feedback) and very good power-supply
rejection (which exceeds 80 dB in
spite of the poor inherent power-supply rejection of a single VCO channel).

Takeaway Points
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Time-encoding VCO-based ADCs
are an interesting ADC architecture in deeply scaled CMOS technologies, as they generally use

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S P R I N G 2 0 2 0	

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digital circuits and frequency-encoded square wave signals rather
than voltage or current linear circuits, resulting in a small area and
good power efficiency.
Open-loop VCO-based ADCs resemble closed-loop delta-sigma modulators in the sense that they behave
as first-order, multibit delta-sigma
modulators. The key system-level
design parameters to achieve a target SQNR performance are the rest
oscillation frequency and sampling
frequency. Here, the phase-domain
model (Figure 6) and corresponding SNR (1) should be the start of
your first design iteration.
To understand more subtle system-level effects (such as overloading and spurious baseband
tones), PFM theory is needed.
To get good distortion and PSRR
performance, a twin setup with
two pseudodifferentially driven
VCOs should always be used in
the basic configuration. In part 2
of this article to be published in
a later issue, more complex architectures for even better performance will be discussed.
To design the core VCO, a PLL architecture style is not the best
approach. Instead, it is important
to think in terms of the input-referred noise of the VCO, leading to
large devices in the VCO core. Designing the VCO mixes traditional
analog amplifier design and VCO
design for PLLs. Hence, it is a craft
of its own.

Acknowledgments
This work was supported by Spanish
Ministry of Science and Innovation project TEC2017-82653-R and the Fund for
Scientific Research Flanders (Research
Foundation-Flanders), Belgium.

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IEEE SOLID-STATE CIRCUITS MAGAZINE	

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