IEEE Solid-States Circuits Magazine - Spring 2021 - 136

T
CEDA Currents
The following is a reprint from CEDA
Currents, April 2021 issue, a publication
of the IEEE Council on Electronic
Design Automation (CEDA).
Please send contributions to Vasilis
Pavlidis (v.pavlidis@ieee.com).
Join the Conversation
on LinkedIn!
We are excited to announce the
launch of a new IEEE CEDA LinkedIn
company page. The CEDA LinkedIn
group page will remain in place for
members to communicate with one
another in a closed setting while the
LinkedIn company page will serve as
a place to find official updates and
communications from the Council.
The new page will allow members
to add CEDA as a volunteer position
on their LinkedIn profile and tag the
Council in posts.
CAD for Assurance Panel:
" Microelectronics Assurance
Under Zero Trust Model "
The IEEE CEDA's Hardware Security
and Trust Technical Committee
developed the " CAD for Assurance "
website and tools for faculty, students,
post docs, and practitioners
in the hardware security community
to disseminate their work. This
initiative also includes a series of
monthly virtual webinars.
The most recent webinar in this
series was a panel titled " Microelectronics
Assurance Under Zero
Trust Model " on 19 April at 11:00
a.m.-12:20 p.m. The webinar was
moderated by Saverio Fazzari and
featured panelists Rob Aitken,
Brian Dupaix, Matt French, and
James Wilson.
Registration is required. For
more information on this webinar
series and to register, visit https://
ieee-ceda.org/cad-assurance.
Call for Papers: IEEE Embedded
Systems Letters Special Issue on
Hardware Security for Post-CMOS
Technologies
IEEE Embedded Systems Letters seeks
to provide a forum of quick dissemination
of research results in
the domain of embedded systems
with a target turnaround time of no
more than three months. The journal
is currently published quarterly
and consists of new, short and critically
refereed technical papers. This
special issue is about attacks and
defenses of the emerging technologybased
embedded systems and covers
several aspects ranging from technology,
circuits,
architecture, automation,
and vulnerability investigations.
Modern societies
are heavily dependent
on electronic
systems. Particularly
with the emergence
of the Internet of
Things and advanced
embedded electronic
devices, such as mobile
computers, wearables,
and smartwatches, personalization
is apparputing
is expected to be in nanostructures
composed of different types of
devices and emerging technologies,
such as ReRAMs, biosensors, MRAM,
and others. In this special issue, we
cover attacks and countermeasures
in future-generation embedded systems
that utilize their nanostructure
composition for security.
Submissions are due 30 July. The
call for papers can be downloaded
from CEDA's website (https://ieee
-ceda.org).
As traditional
2D scaling is
there is great
motivation to
approaching its
physical limit,
explore the 3D for
future integrated
circuit design.
ent. The rise of the electronic device
jungle has provided a large attack
surface to bad actors to manipulate
hardware and processed information.
The attacks can significantly
affect the three foundational aspects
of secure hardware: confidentiality,
integrity, and availability. These
cornerstones of hardware security
in embedded systems are in danger
of physical and remote attacks by
adversaries during different periods
of their design and lifecycles.
Depending on the attack, the counDigital
Object Identifier 10.1109/MSSC.2021.3072330
Date of current version: 24 June 2021
136 SPRING 2021
termeasure can also be innovative
and wide in range. The future of comIEEE
SOLID-STATE CIRCUITS MAGAZINE
Call for Papers: IEEE Journal on
Exploratory Solid-State Computational
Devices and Circuits Special Issue
on Monolithic 3D Integration for
Energy-Efficient Computing
As traditional 2D scaling is approaching
its physical limit, there is great
motivation to explore the 3D for future
integrated circuit design. The memory
industry has already adopted monolithic
3D integration (e.g., in 176-layer
3D NAND Flash) while
the 3D vertical integration
structure of logic
transistors (e.g., 3D
stacked nanosheets,
NMOS on top of PMOS)
is emerging for sub3-nm
logic nodes. The
other trend is to stack
the embedded nonvolatile
memories (e.g.,
RRAM, PCM, MRAM,
FeFET) on top of CMOS using backend-of-line
processing.
Taking it one step further, the
integration of multiple tiers of active
transistors with embedded memories
is expected to offer significant
improvements of throughput and
energy efficiency thanks to the massive
connectivity between logic and memories.
Besides the technological breakthroughs,
circuit design automation
methodologies become key enablers
to optimizing the tier partitioning in
monolithic 3D architectures. In addition,
heat dissipation should be taken
care of by accurate thermal modeling
https://ieee-ceda.org https://ieee-ceda.org https://ieee-ceda.org/cad-assurance https://ieee-ceda.org/cad-assurance
IEEE Solid-States Circuits Magazine - Spring 2021

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