IEEE Solid-States Circuits Magazine - Spring 2021 - 16

SHOP TALK: WHAT YOU DIDN'T LEARN IN SCHOOL
Chris Mangelsdorf
Oscillation and Ringing
Finding Worst-Case Capacitive Load
I
What, Me Worry?
It's a universal problem: How do you
design an analog block when you
don't know exactly what the capacitive
load is going to be? It is disconcerting
how often this problem
comes up. In the old days, there was
always the threat that the customer
would hang something ill-advised
on your output pin. Today's systemon-chip
(SOC) environment shelters
most functional blocks from the
application board, but you could still
be blindsided by wiring capacitance
on the chip itself. Basically, you
won't know how much capacitance
will be clinging to your creation until
the layout is nearly finished, and it
could change at the last minute.
Even if you survive layout, the
real minefield is this: blocks get
reused. Borrowed cells are often
blindly pressed into service without
the original designer's knowledge or
approval.
Ironically, simple blocks
or blocks with some unglamorous
function are most likely to cause
trouble. Such modest blocks inspire
complacency and are far more likely
to be reused and less likely to be
reengineered for their new application.
So a perfectly good design
could come back to haunt you when
it appears in an environment you
never anticipated.
It's also possible that you will
find yourself on the receiving end:
How can you be sure the block you
Digital Object Identifier 10.1109/MSSC.2021.3072801
Date of current version: 24 June 2021
16
Welcome to " Shop Talk " !
This column aims to provide streetwise circuit savvy for real-world problems. Design cheats,
myth busting, technical insights, career advice, and " stupid FET tricks " are all on the agenda.
To keep things relevant and entertaining, though, I need your feedback. Send your suggestions,
comments, questions, and-should the unthinkable happen-corrections to me at shifobrains@
ieee.org.
-Chris Mangelsdorf
borrowed from another design is not
going to turn your massive SOC into
an expensive oscillator? (Career tip:
Pointing the finger at the original
block designer in this case will not
get you off the hook or bring your
chip back to life.) What to do?
Of course, adding capacitance
to an analog output slows it down,
but that's no mystery. You
are well-aware of your bandwidth
sensitivity to capacitive
load as soon as you
wade into any high-frequency
design. Oscillation,
on the other hand,
is much more tricky. Did
you know that a circuit
can be stable with both
light and heavy loads
and yet ring like a bell
when loaded with some intermediate
value capacitor? (That got your
attention, didn't it?) So what are
you going to do-simulate with all
possible loads?
What follows is a simple technique
put, from microwave
amplifiers to
Did you know
that a circuit can
be stable with
both light and
heavy loads and
yet ring like a
bell when loaded
with some
intermediate
value capacitor?
dc voltage references. Here, we focus
on capacitive loads because they are
the most common unknown. With
some modification, though, the technique
can be used with all kinds of
loads. And of course, the technique
can be applied to nodes which are
not considered outputs but nevertheless
may be subject
to unknown loading.
With a fast simulator,
you could certainly
try a lot of load combinations,
so why do you
need this? Here's why:
Blind parameter sweeps
don't tell you what to do
next. When you find a wide
range of capacitance that
makes your circuit ring or
for determining performance over all
loading in one shot. It can be useful
for anything that has an analog outSPRING
2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
oscillate (and you almost certainly
will), what are you going to do about
it? The real payoff of the technique
presented here is that you will know
precisely what it is about your design
that is making it vulnerable. This
approach not only tells you when
something is wrong; it also tells you
how to fix it. You're welcome.

IEEE Solid-States Circuits Magazine - Spring 2021

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