IEEE Solid-States Circuits Magazine - Spring 2021 - 31
means to significantly reduce power
consumption in cryogenic SiGe LNAs.
Following these exciting results,
we formed a collaboration with the
Harvard Smithsonian Center for Astrophysics
aimed at developing scalable
terahertz receiver front ends. To
this extent, we iteratively developed
a single-pixel receiver consisting of a
220-GHz SIS mixer chip, directly connected
via a 1-mm-long, 125- mn diameter
beryllium copper (BeCu) wire to a
discrete transistor SiGe intermediate
frequency (IF) LNA.
After first demonstrating that a
properly designed SiGe amplifier
can be directly connected to an SIS
mixer without an intermediate isolator
[71], [72], we went on to demonstrate
the complete single-pixel
receiver portrayed in Figure 9(c) [69].
Remarkably, this circuit required just
3Wn for proper operation while
providing similar system noise performance
[Figure 9(d)] in comparison
to the same SIS mixer connected to a
standard amplification chain (including
an isolator between the mixer and
the amplifier, the latter of which drew
15 mW). This result is significant in
that the demonstrated single-pixel
system is of low enough power consumption
to enable a kilopixel-scale
terahertz focal plane array system.
Building on these initial results,
00
we have focused our subsequent
efforts in two key areas: further
reducing the noise and demonstrating
low-power ICs with similar performance
to that realized with discrete
transistors. To explore the limits of
the noise performance of low-power
SiGe cryogenic LNAs, we formed a
collaboration with Innovations for
High Performance Microelectronics
(IHP), who developed a variant of the
SG13G2 technology optimized for
low noise at cryogenic temperatures
[50]. These transistors featured both
special doping profiles in the base
and emitter regions a modified Ge
profile. When biased at a collector
current density of 0.5 mA/μm2 and
cooled to 7 K, the optimized transistors
featured DCb and ft
values of
17,000 and 350 GHz, respectively.
Moreover, from the experimentally
extracted model, the technology
achieves T 1KMIN
. at 5 GHz, which is
just a factor of eight above the standard
quantum limit.
A proof-of-concept 4-8-GHz discrete
transistor amplifier dissipating
just 1 mW and achieving 25dB2
of gain was fabricated using these
transistors; a photograph of the
(a)
(c)
10
f = 3 GHz
2
4
6
8
290 µW
180 µW
0 0.1 0.2 0.3 0.4 0.5
VCC (V)
(b)
20
40
60
80
2
3
4
5
6
7
8
IF Frequency (GHz)
(d)
9
10
100
660 µW
370 µW
300 µW
230 µW
10
7
8
9
fLO = 220 GHz
1
2
3
4
5
6
23 45 67 89 10
Frequency (GHz)
(f)
FIGURE 9: Low-power discrete transistor circuits. (a) A proof-of-concept 290-nW, 1.8-3.6-GHz cryogenic LNA achieving a noise temperature
between 3.4 and 5 K over the entire passband when operated at a physical temperature of 15 K [67]. (b) The dependence of noise of the
proof-of-concept 3-6-GHz LNA at 3 GHz on Vcc. The amplifier noise only depends weakly on Vcc for voltages as low as 125 mV (PDC = 180 nW).
(c) A hybrid SiGe/SIS single-pixel receiver [69]. The SiGe amplifier is impedance matched to the IF output impedance of the SIS mixer and
connects to the mixer chip via a 1-mm BeCu wire with a diameter of 125 nm. (d) The double-sideband IF noise temperature of the single pixel
receiver for different amplifier power consumptions when driven with a 220-GHz local oscillator and thermalized to a physical temperature of
4.2 K. The nominal power consumption of 300 nW is sufficiently low to comfortably permit the realization of a 1,000-pixel dual polarization
terahertz focal plane array system under the power budget associated with a single 4-K cryogenic cooler. (e) A prototype 4-8-GHz cryogenic
LNA using noise optimized HBTs [50]. (f) The noise performance of the 4-8-GHz amplifier at a power consumption of 1 mW. The noise performance
of this circuit at 8 GHz was about two times lower than the previous state-of-the-art SiGe cryogenic LNA [70].
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2021
31
(e)
Noise (K)
Receiver Noise (K)
Noise (K)
IEEE Solid-States Circuits Magazine - Spring 2021
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2021
Contents
IEEE Solid-States Circuits Magazine - Spring 2021 - Cover1
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