IEEE Solid-States Circuits Magazine - Spring 2021 - 39

substantially higher signal-to-noise
ratio (SNR) at LAr temperature than at
room temperature. Moreover, mounting
the readout electronics in close
proximity to the sensor minimizes the
input capacitance, which is typically
the dominant factor for noise (see
the " Cryogenics Electronics at Scale "
section). These factors are especially
important for detectors without intrinsic
gain, such as single-phase LAr TPCs,
which require low-noise electronics to
achieve sufficient SNR to perform both
calorimetry and particle identification,
based on the measurement of energy
loss per unit pathlength ( /dE dx).
Cryostat Design
As argued in [18], possibly the foremost
benefit of having cryogenic electronics
operating within the detector is
the freedom it affords in the design of
large and complex cryostats. The high
degree of multiplexing obtainable with
multichannel ICs greatly reduces the
number of signal links and cryostat
feedthroughs, the position of which
can be optimized based on the cryostat
design, without the need to be close
to the sensors. In the case of warm
readout electronics, on the other hand,
limiting the number of signals exiting
the cryostat would require compromises,
such as very long drift distances
(resulting in very stringent purity
requirements to avoid charge recombination
and signal degradation), very
long sense wires, or wires connected
in series, degrading the detector sensitivity
through attenuation of the signal
charge during long drifts and the
increased electronic noise associated
with the cables, resistance and capacitance.
Long wires and cables are also
susceptible to microphonic and electromagnetic
pickup.
Reliability and Stability
After the cryostat is filled with LAr,
the cryogenic electronics cannot be
serviced or replaced and must operate
reliably for the duration of the
experiment
(>20 years for DUNE).
As discussed in the " Lifetime " section,
the lifetime of the IC under the
heightened hot-carrier degradation is
Low-Power Dissipation
A low-power design is necessary to
avoid large cross-section power cables,
a major design consideration. For testing
purposes, packaging and bonding
must also survive repeated thermal
cycling [15]. Electrostatic discharge
(ESD) damages, which after installation
could result in permanent loss
of operating channels in the detector,
are mitigated by the adoption of standard
ESD protection in the ASICs and
by adhering to best practice during
handling and assembly.
Redundancy and Risk Mitigation
Following directly from the earlier consideration,
cryogenic ICs often employ
extra redundancy and configurability.
The aforementioned ADC ASIC [16],
for example, employs both a bipolar
junction transistor (BJT)-based and
a CMOS-based on-chip reference circuit.
Slow controls were implemented
using redundant data paths, one using
I2C and one using a custom universal
asynchronous receiver-transmitter.
Operation Across Temperatures
Prior to installation, all readout modules
are to be characterized immersed
in liquid nitrogen (LN2), which, with a
boiling point of 77 K not far removed
from that of LAr, provides a more
abundant and cost-effective way of
testing the large number of ASICs
involved (54 k in the case of one of
the four DUNE LAr TPCs). It is, however,
highly desirable for cryogenic
ICs to also be functional at room
temperature, as this greatly simplifies
screening and prototype testing.
Cryogenic ASICs are thus often highly
programmable to optimize performance
across a wide range of temperatures.
The data concentrator IC, for
example, was designed with extended
selectable phase locked loop (PLL)
range to cover both cryogenic and
room temperature operations; its two
1.28-Gb/s line drivers with preemphasis
were also validated with both
cold and room temperature 25-m and
35-m twinax cables to verify insertion
losses and data rates [16].
as well as temperature gradients that
may lead to excessive convection or
to the formation of bubbles of gaseous
Ar, which could break down the
high-voltage biasing of the detector.
The current design prevents boiling
by a safety factor of 20 in terms of
total power (35 mW/channel) and at
least two in terms of power density.
A perforated mechanical box enclosing
the cryogenic electronics, which
also provides mechanical support
and cable strain relief, further controls
potential boiling by channeling
bubbles through two side tubes to the
top of the cryostat. An interesting lowpower
solution is presented in [19],
where the adoption of self-trigger digitization
and daisy-chain multiplexing
readout in a 32-channel cryo ASIC
(180-nm CMOS) resulted in a power
consumption below 100 μW/channel.
This figure is compatible with a TPC
design based on a pixelated array
of charge-sensitive pads (instead of
sensing wires), which has advantages
for high-occupancy detectors.
Radiopurity and Outgassing
(for Low Background Experiments)
While it is difficult to produce ultralow
background cables, in several instances
silicon devices have been measured to
have extremely low background contamination.
Contamination from outgassing
also generally limits the use
of discrete components and favors IC
solutions [3].
Cryogenic Characterization
of CMOS Devices
With foundry transistor models generally
guaranteed only above 233 K,
the design of complex low-noise, lowpower
analog and mixed-signal IC
relies on the availability of dedicated
cryogenic device models. These models
must accurately capture static,
dynamic, and noise responses across
operating regions (strong, moderate,
and weak inversion). While there is a
vast amount of literature in this field
(e.g., [20]), the models available within
the HEP community are the results of
targeted efforts by a few ASIC design
groups at National Laboratories, who
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2021
39
IEEE Solid-States Circuits Magazine - Spring 2021

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