IEEE Solid-States Circuits Magazine - Spring 2021 - 40

developed process-specific test structures
and isothermal models targeting
operation in LN2, LAr, and LXe.
These and similar activities have
seen renewed interest with the recent
rise in quantum information and
technology research, for which the
development of ICs operating at 4 K
and below is becoming increasingly
prominent (e.g., [21], [22]). At these
deep-cryogenic temperatures, mature
technologies (>130-nm CMOS) can
exhibit nonidealities due to a combination
of impact ionization, body effect,
and freezeout of the bulk caused by
insufficient dopant ionization from
thermal energy. The heavy/degenerate
doping and bandgap engineering of
nanometer CMOS processes, however,
allows operation below temperatures
associated with the freezeout of lightly
to moderately doped silicon (70-40 K).
10
8
6
4
2
101
100
10-1
10-2
10-3
10-4
10-5
0.3
DC Characteristics
Figure 4 compares the simulated and
measured dc characteristics of an
NMOS in 180-nm CMOS at 300 K and
at 77 K. Good agreement at room
temperature was as expected; some
differences in the saturation voltage,
subthreshold slope, and transconductance
at 77 K were observed
and demonstrated the need of cryogenic
models, especially for transistors
working in weak inversion and
the transition region between linear
and saturation regions.
Noise
Noise analysis for low-noise frontend
readout for HEP detectors commonly
employs the classical model
in (1) for input-referred noise spectral
density of the input MOSFET
[13], [23], [24], which in many cases
Simulated (Foundry Parameters)
77 K
300 K
CMOS018
0.3
0.6
NMOS, L = 0.18 µm, W = 10 µm
1.5
0.9
VDS (V)
CMOS018 gm
ID
Simulated
(Foundry Parameters)
77 K
300 K
101
100
NMOS, L = 0.18 µm, W = 10 µm
0.6 0.9
1.2
VGS (V)
10-1
10-2
10-3
10-4
10-5
1.5 1.8
0.3
CMOS018
gm
ID
Measured
77 K
300 K
1.2
10
8
6
4
2
1.8
is one of the dominant noise contributors:
Svn=+fa
ox
CWLf
K
f
aw
4kTnc
gm
.
(1)
The
1/f noise contribution depends
on the 1/f noise coefficient Kf, the
oxide capacitance per unit area Cox,
the transistor width W and length L,
the operating frequency f, and the
1/f noise slope factor af. The white
noise contribution depends on the
noise excess coefficient aw, temperature
T, the subthreshold slope factor
n, an inversion-re lated coefficient
c , and transistor trans conductance
g. For cryogenic oper ation, transistor
operating para meters n,
c ,
and gm can be either simulated or
extracted from dc measurements of
individual devices, while the noise
coefficients Kf, af, and aw are often
Measured
CMOS018
77 K
300 K
0.3
0.6
NMOS, L = 0.18 µm, W = 10 µm
1.5
0.9
VDS (V)
1.2
1.8
0.6 0.9
NMOS, L = 0.18 µm, W = 10 µm
1.2
VGS (V)
FIGURE 4: The simulated and measured dc characteristics of an NMOS in 180-nm CMOS at 300 K and at 77 K [13].
40
SPRING 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
1.5 1.8
ID (mA), gm (mS)
ID (mA)
ID (mA), gm (mS)
ID (mA)
~72 mV/dec (In(10)nVT)
~72 mV/dec (In(10)nVT)
~18 mV/dec
~18 mV/dec
IEEE Solid-States Circuits Magazine - Spring 2021

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