IEEE Solid-States Circuits Magazine - Spring 2021 - 43

one can choose the optimal weighting
function for a front end. The LAr TPC
front end in [13] implemented a fifthorder
semi-Gaussian analog shaper,
while the germanium point-contact
detector in [31] employed a digital triangular
shaper for an extremely lownoise
requirement.
Since the input transistor plays a
dominant role in the front-end ENC,
optimizing the size, power, and
transcoductance of the input transistor
is a must to achieve optimal ENC.
Examples of optimizing ENC versus
input MOSFET size and power for
the LAr TPC front end can be found
in [13]. The measured ENC from the
first ASIC prototype showed higher
white noise contribution than simulation,
due to thermal noise from
the parasitic resistance of the ASIC
input lines (~12 Ω) and the dielectric
loss from the input capacitor emulating
the wire capacitance in the test
setup. The revised ASIC achieved
very good noise performance, and
8,256 front-end channels out of 516
ASICs have been installed in a 170-ton
LAr TPC for MicroBooNE detector.
A comprehensive noise characterization
of the full detector can be found
in [34]. The actual temperature of
the devices in an ASIC would in general
be a few degrees higher than the
cryostat temperature due to finite
thermal resistance. The degradation
on the achieved noise performance
depends on the dominate noise
contributions and has been found
negligible in applications where 1/f
noise dominates.
High-Resolution ADC
The LAr HEP detectors presented in
the " Low-Power, Low-Noise Analog
Front End " section require high-resolution
(~12 b) ADCs to ensure accurate
data reconstruction of weak signals.
However,
it has been challenging to
achieve high resolution in cryogenic
operation, due to the lack of cryogenic
device mismatch models since mismatches
of active devices are worse
compared to room operation [35], [36].
Early efforts on high-resolution cryogenic
ADCs include a 12-b dual-stage
Charge Amplifier
ls =
Cc
Cf
li = Acli
current-mode ADC implemented in a
180-nm process [13], which, however,
suffered from linearity degradation
from room to cryogenic operation. Mismatches
among the least significant bit
(LSB) current sour ces were a main concern.
A successive approximation register
(SAR) ADC architecture was later
implemented in 65 nm, considering
that the mismatches of passive capacitors
would be relatively consistent at
room and cryogenic temperatures,
100
80
60
40
20
-20
-40
-200 -150 -100
-50 050
Difference (ps)
FIGURE 6: A comparison of timing libraries characterized at room temperature and cryogenic
temperature, where the difference of the delay was plotted against its percentage change [16].
100
and perturbation-based digital background
calibration was applied to
compensate for capacitor mismatches
[37]. Redundancy was built into the
metal-insulator-metal capacitor digitalto-analog
converter (DAC) with 14 segments.
In simulation, capacitor mismatches
were set randomly, and the
perturbation signal was selected as
10 LSBs. Optimal capacitor weights were
obtained after calibration. Simulation
results demonstrated that missing codes
Vth Dominated
Mobility Dominated
R1
Cf
li
Cc
-∞
-∞
First Pole
V1 = Z1ls =
Additional Poles
Shaper
AcR1
1 + sR1C1
li
FIGURE 7: A schematic of a low-noise analog front end including a charge amplifier with
capacitive feedback and a shaper with a transimpedance input stage (where ideal op-amps
were assumed) [32].
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2021
43
Is
Vo
C1
V1
Ratio of Difference (%)
IEEE Solid-States Circuits Magazine - Spring 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2021
