IEEE Solid-States Circuits Magazine - Spring 2021 - 51

in Figure 3(a), the parasitic capacitance
at the quantum point contact
(QPC) node is minimized to increase
the voltage swing due to the arrival/
departure of one electron. In contrast
to the conventional creation of
QDs entirely through process lithography,
our QDs are defined mainly by
the applied voltage potentials at the
imposers. Since the control voltages
can be precisely set in time and amplitude,
as demonstrated in Figure 4,
the depths of the quantum wells and
the tunneling between them can
precisely control the movement of
individual electrons and their mutual
entanglement for the intended
quantum operation. A simulation of
such movement is shown in [30]. The
load presented by the QDA is capacitive
and very light. Hence, the driving
circuits in Figure 4 can dissipate power
in the range of tens of microwatts
and still operate at the gigahertz rate
while providing precisely controlled
voltage levels and pulses of ultralow
amplitude noise (note that the tunneling
rate is exponentially related
to the imposer's voltage [14]).
Figure 5 illustrates further details
of the electronic interface to the quantum
core, acting as a reset, control,
single-electron injector and detector.
Capacitive digital-to-analog converters
(DACs) control the precise amplitude
and timing of the pulses for 1)
the reset operation (RD
and RG
vide a high-resolution amplitude setting
for the quantum control pulses.
The pulse amplitude sets the Rabi
oscillation frequency in the semiconductor
quantum structures, while the
pulsewidth determines the particular
quantum operation that is performed,
such as a quantum controlled NOT
gate, quantum rotation, Hadamard
split, and so on. The quantum detectors
are followed by correlated double
samplers that provide first-order correlated
noise rejection. After further
amplification and analog-to-digital
conversion, the detected signals are
sent to the field-programmable gate
array (FPGA) board. Individual perqubit
calibration loops are used to set
the appropriate pulse amplitude and
width levels for each local quantum
structure. This compensates for the
CMOS process variation impact on the
quantum performance of each qubit.
Takeaway Points
■ Quantum computers promise to
solve currently intractable problems
in mathematics, chemistry,
material science, and other areas.
■ The recent barrage of cryo-CMOS
circuits has been spurred by the
need to build a practical quantum
computer.
■ CMOS technology offers a fantastic
opportunity for integration,
scalability, and mass production,
thus motivating research in silicon
qubits.
High-Speed Pulse Generator
2-GHz
Clock
300 K
FGPA
ADC
ADC
Reset
RG
SPI
VDET
d1
dx
d1
Detector
(a)
signals)
to ensure that the QPC node is
free from extra electrons, 2) singleelectron
injection into the first QD,
and 3) imposers to transfer electrons
between the QDs.
The Quantum SoC
Figure 6 diagrams the quantum SoC
[25] realized in 22-nm FDSOI and operating
at ~4 K. A 2-6-GHz external
clock is buffered and divided down
to create a multiphase system [31],
while the pattern generator core determines
the selection of the appropriate
clock edges to create the fast
and narrow pulses needed to control
the quantum structures. The pulse
generator provides high-resolution
pulsewidth control, while DACs proImposer
Gate
RG
RD
VQPC
VDET
Reset On
Reset Off
QPC Snapshot 1
Imposer Pulse
QPC Snapshot 2
Readout
(b)
FIGURE 5: The (a) interface circuitry to the QDA, with (b) a timing diagram of the signals.
The QDA is schematically represented as a chain of single-electron transistors (SETs) consisting
of coupled QDs with controllable tunneling. ADC: analog-to-digital converter; SPI: serial
peripheral interface; RG: reset gate; RD: reset drain.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2021
51
Mirror Image
Quantum Core
RD
QPC
Pattern
Generator
Imposers
....
Reset
QPC
d2
Detector
....
....
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC

IEEE Solid-States Circuits Magazine - Spring 2021

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