IEEE Solid-States Circuits Magazine - Spring 2022 - 58

word line (WL). This structure is
known as a page (colored in blue),
and finally, a set of strings is called a
block (brown box).
Oxide
Traps
Interface
Traps
6
4
2
Tunnel
Storage
Node
Si Substrate
Oxide
(a)
-2
-4
100 101 102 103 104 105 0.5
Cycles (Number)
(b)
FIGURE 2: The reliability issues of a flash memory cell. (a) The trap/detrap of unwanted electrons
and (b) operation window degradation by reliability issues. Si: silicon.
WLs
SSL
WLn-1
WLn-2
Cell
WL1
WL0
GSL
BL0 BL1 BL2 BL3 BLm-3 BLm-2 BLm-1
. . .
CSL
BLs
(a)
String
Page
Block
Baking Time (hr)
If one looks at the cross-sectional
view of a string [Figure 3(b)], it will
be clear that there are only two contacts,
one each at both ends of the BL
85 °C Endurance
Narrower Window
(By Endurance)
250 °C Bake
Vth Shift Down
(By Retention)
6
4
2
-2
-4
1 1.5 2
and CSL [10]. In addition, no contacts
are used to form a page; they are connected
using a WL. Finally, all the cells
in a block share a single-pocket p-well.
Thanks to these unique structural
advantages, it is possible to realize a
cell size close to 4 F2, which is the ideal
lower limit of a memory cell size; thus,
an NAND flash memory shows superior
areal density and incomparable
cost competitiveness when compared
to other types of memory.
History of the NAND Flash:
A Bird's-Eye View
In the previous section, the basics of
an NAND flash memory were briefly
covered. Here, an examination of the
history of NAND flash technology,
from its invention, to the present,
and some of its defining moments, is
now offered.
Figure 4 depicts the 38-year-long hisTop
View
A
BL Contact SSL
WL
Cross-Sectional
View (A-A′)
BC D
BL
Cross-Sectional
View (B, C, and D)
Storage Node
(b)
FIGURE 3: (a) The string, page, and block of an NAND cell array and (b) a cross-sectional
view. WLs: word lines; CSL: common source line; BLs: bit lines; SSL: string select line; GSL:
ground select line.
58
SPRING 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
WL
Source Line
Cell
GSL
Source Line
2F
2F
A′
tory of NAND flash memory. The data
are extracted from papers published in
the IEEE International Electron Devices
Meeting, International Solid-State Circuits
Conference, VLSI Circuits Symposium,
and several other meaningful
events [4]-[42]. The whole period is
divided into three major parts: the first
is its invention; the second, 2D NAND;
and the third, 3D NAND. The basic
operation concept of flash memory was
presented for the first time in 1984 [4].
In 1995, NAND flash finally succeeded
in commercialization [8]. The first product
was a 32-Mb, single-level cell device
based on a 470-nm process. Six years
later, 2D (planar) NAND surpassed 1 Gb
in its density [11], and multilevel cell
(MLC) products that store 2-bit per cell
were successfully deployed [10]. After a
rapid evolvement of more than 10 years,
3D vertical NAND (V-NAND), a disruptive
technology, first appeared on the market
in 2014. This history of continuous
innovations was possible with the help
of numerous breakthrough technologies
in various areas such as materials,
process integration, circuits/algorithms,
and system-level management.
First Phase: Invention
In 1984, the concept of " Flash EEPROM "
was first presented by Masuoka et al.
Threshold Voltage (a.u.)
IEEE Solid-States Circuits Magazine - Spring 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2022
