IEEE Solid-States Circuits Magazine - Spring 2022 - 59

Invention
2D (Planar) NAND
106
105
104
103
102
101
100
SLC
MLC
TLC
QLC
First CTF QLC V-NAND (Samsung, ISSCC 2018, 1 Tb)
First V-NAND (Samsung, ISSCC 2014, 24 WL)
First TLC V-NAND (Samsung, ISSCC 2015, 128 Gb)
First TLC Mass Production
(SanDisk, ISSCC 2008, 16 Gb, 56 nm)
3D NAND
QLC
TLC
(Samsung, ISSCC 2021,
512 Gb)
TLC (Toshiba, ISSCC 2009, 32 Gb, 56 nm)
First 1-Gb MLC (Samsung, ISSCC 2001, 1 Gb, 120 nm)
First Flash (Toshiba,
ISSCC 1985, 256 Kb)
MLC - LSB/MSB Concept (Toshiba, VLSI 1997, 128 Mb)
First MLC Concept (Samsung, ISSCC 1996, 128 Mb, 400 nm)
First Mass Production (Samsung, ISSCC 1995, 32 Mb, 470 nm)
1985
1990
FN Tunneling (Toshiba, IEDM 1990)
1995
2000
2005
2010
2015
2020
2025
FIGURE 4: The history of NAND flash development: a bird's-eye view. SLC: single-level cell; QLC: quadruple-level cell; CTF: charge-trapped
flash; MLC: multilevel cell; TLC: triple-level cell; V-NAND: vertical NAND; ISSCC: International Solid-State Circuits Conference; VLSI: VLSI Circuits
Symposium; IEDM: IEEE International Electron Devices Meeting.
[4]. The proposed EEPROM cell consists
of three terminals: a floating gate
for data holding, control gate for cell
selection, and a gate for erase operations.
We should note that erase gates
of cells are connected in common. As a
result, all of these are erased together
at the same time, i.e., all data are gone
in a " flash " moment. This is the reason
Masuoka named this device flash. He
also demonstrated a chip with 256 Kb
of density based on a 1.2-µm design
rule in 1985 [5]. A few years later, the
concept of an NAND string structure
was presented for the first time [6], [7].
It featured two select transistors for a
string, and a double-well structure for
noise separation between a cell array
and a peripheral circuit.
Although many technological
achievements had been made since its
first appearance, there were two crucial
hurdles to overcome for commercialization.
The first one was a high-voltage
(HV)-related issue: nearly ~30 V
should be directly applied to WLs and
BLs. Therefore, flash cells and related
selectors were not able to be scaled
down. In addition, the circuit size
needed to generate the corresponding
voltages had to be large, which played
as a major hurdle in increasing the
PGMInhibited
BL
SSL
(VCC)
Vpass
Vpass
Vpgm
V
0 V
0 V
10 V
10 V
18 V
GSL
(0 V)
BL
(VCC)
VControl_Gate
CONO
CTunnel
CChannel
VCh
Si Substrate
BL
(GND)
(a)
Control Gate
ONO
Storage Node
Tunnel Oxide
VCh =
Channel
(b)
FIGURE 5: A self-boosting scheme. (a) A newly defined operation bias and (b) the concept of
capacitive coupling at a channel. PGM: program; GND: ground Si: silicon; S: source; D: drain.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2022
59
Cins =
CONO CTunnel
CONO+
~8 V
SD0 V
VProgram
<20 V
SD
~8 V
PGM
BL
VProgram
~18 V
CTunnel
Cins
Cins+
Cchannel
VControl_gate
Density (Mb)
IEEE Solid-States Circuits Magazine - Spring 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2022
