IEEE Solid-States Circuits Magazine - Spring 2022 - 61

lower program voltage, and slow cells
to be programmed with a higher program
voltage, which resulted in much
narrower Vth distribution. As depicted
in Figure 6(c), the fast cell was sufficiently
programmed at loop 2. After
that, it is automatically switched to a
" program-inhibit " state so that the cell
is not affected by subsequent higher
voltages for the slow cell programming
anymore. As a 1-V increment of
the voltage was proven to be approximately
as effective as a five-times
increment of the time duration with
a fixed voltage level [8], [9], the time
needed for completing the programming
operation became shorter, which
resulted in a high writing performance.
Second Phase: 2D (Planar) NAND,
a Period of " Big Bang "
With the help of these two key enablers,
2D (planar) NAND entered a period of
full-scale progress-known as a period
of Big Bang. During this time, the density
of an NAND device was doubled
every two years (see Figure 4). These
advances had been driven by two major
technology trends: continuous cell scaling
and multibit/cell technology.
Figure 7 shows a trend of cell scaling.
Cell size had been reduced to onethirtieth,
and the device's density had
increased by more than 1,000 times over
20 years. The first product was based
on 470-nm technology and had 32-Mb
density [8], but around 2014, 128-Gb
devices based on 16 nm were commercialized
[22]. Advances in lithography
were one of the main drivers for this
trend. ArF-based lithography processes
started to be adopted from ~100-nm
technology nodes. In addition, doublepatterning
technology was deployed
from ~30-nm node to overcome the
technical limitation of single patterning,
while maintaining the production
cost at a reasonable level [20].
Along with cell scaling, multibit technology
also played a key role. MLC technology,
which stores 2-bit in one cell,
became mainstream in the marketplace
in the early 2000s [12], and triple-level
cell (TLC), 3-bit-per-cell technology was
launched circa 2008 [17]. As TLCs could
achieve up to a 50% more areal density
compared to MLCs in theory, they were
accelerators for more bit/areal density
and cost/bit reduction.
The second trend was driven by
many innovative ideas from various
fields for overcoming the cell-to-cell
interference phenomenon, which is
definitely one of the most serious
Control Gate
ONO
1
Substrate
BL (1) BL (2) BL (3)
WL (i+1)
WL (i)
4
2
3
1
4
2
WL (i)
Vth
(a)
Available Vth Window
Aggressor
2 3 4
1
WL (i+1)
2 3 4
Victim
problems in NAND flash. As displayed
in Figure 8(a), the unwanted electrical
influence for each other becomes
worse as the distance between adjacent
cells becomes shorter by scale down.
Number of electrons stored in a cell
is also dramatically reduced. For
example, the amount of interference in
MLC
(2 bit)
Vth
TLC
(3 bit)
(b)
Vth
FIGURE 8: (a) Cell-to-cell interference. (b) A comparison of operations for MLC and TLC.
TABLE 1. TECHNIQUES FOR OVERCOMING INTERFERENCE.
TECHNIQUES
Shadow program [10]
All-BL program [16]
Dual-pulse program [23]
Data randomizing [25]
Data recovery [15]
Negative Vth control [19]
W-gate, BL air gap [20], [21]
Reprogram [14]
OBP [24], [26]
OBP: on-chip buffering.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2022
61
INTERFERENCE DIRECTION
WL
BL
BL
WL/BL/diagonal
WL
WL/BL/diagonal
WL/diagonal
WL/diagonal
WL/BL/diagonal
63-nm MLC
-
-
35-nm MLC
-
27-nm MLC
-
27-nm TLC
-
FIRST SHOWN
(AT PRODUCT)
IEEE Solid-States Circuits Magazine - Spring 2022

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