IEEE Solid-States Circuits Magazine - Spring 2022 - 64

CG
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(a)
FIGURE 14: The future 3D NAND candidates for higher areal density. (a) A split-gate cell and (b) programmable logic controller (5-bit per cell).
Si: silicon; SiO: silicon dioxide.
as mold height is decreasing. Continuously
increasing manufacturing costs
is also a big issue. The challenges 3D
NAND is facing are briefly summarized
in Figure 12. Further discussions on
this subject can be found in [44].
Future Trends
From now on, let us take a look at
future candidates of NAND flash. Stateof-the-art
3D NANDs are increasingly
adopting cell-on-peri (COP) technology
[41], [42]. As shown in Figure 13,
it is literally a technology that places a
cell array " on " a peripheral circuit and
connects it using through-hole vias.
In this case, the chip size is dramatically
reduced as most of the peripheral
circuit, whose area portion is roughly
20~30%, can be hidden. In addition,
enhancing performance becomes
easier because more circuits can be
added under the array. For example,
most COP-based 3D NAND devices are
adopting four-plane architectures by
adding more PBs at the vacant area
under the cell array. In this case, the
read/write performance of the COPbased
device is doubled, compared
to conventional two-plane devices.
However, the problem is the manufacturing
cost. As the peripheral circuit
and cell array must be implemented
separately, the total number of process
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SPRING 2022
steps should be increased by at least
30%. The increased design complexity
also poses hurdles to be overcome.
The place-and-routing plan should be
carefully designed to efficiently connect
the upper and the lower circuits
while satisfying several constraints
such as signal integrity (time delay,
voltage drop, and crosstalk). Finally,
new issues such as mechanical stress
must be addressed adequately.
Along with COP, technologies for
increasing bit area density are being
continuously researched. Split-cell
technology, introduced in 2019, is a
good example [43]. It physically splits
the existing cylindrical cell in half and
searches for the possibility of a 5 bit/cell,
as illustrated in Figure 14. If this technology
succeeds, a drastic jump in terms of
areal density can be achieved; however,
many new technical challenges are anticipated.
For example, an unprecedented
level of error-correction capability may
be mandatory for an NAND controller
to overcome a near-zero-operation margin
among Vth distributions, which may
result in side effects on the total power
and cost of a storage system.
Conclusion
In this article, the 38-year journey
of NAND flash, from its beginning to
its possible future, was presented by
IEEE SOLID-STATE CIRCUITS MAGAZINE
touching on some defining technical
challenges and innovations the NAND
industry has undergone thus far. It
is obvious that NAND flash, as it has
done previously, will play a key enabler
in the upcoming data-centric era. This
means that the future prospects of the
NAND industry is very positive, and its
upward trend is expected to accelerate.
Therefore, I can confidently proclaim
that now is the time to prepare another
disruption, just like 3D NAND did eight
years ago. The possibilities are truly
endless and widely open to all of us.
References
[1] " Changing the way the world thinks
about the impact of technology on business
and society, " IDC, Needham, MA,
USA. [Online]. Available: https://blogs.
idc.com/2019/09/04/how-idcs-industry
-cloudpath-saaspath-surveys-can-inform
-your-cloud-saas-strategy/
[2] Y. Kojima, M. Kamiya, K. Tanaka, K. Nagai,
and Y. Hayashi, " New instability in thin
gate Oxide MOST's, " in Proc. Int. Electron
Devices Meeting, 1981, pp. 392-395, doi:
10.1109/IEDM.1981.190096.
[3] H. Yang et al., " Reliability issues and
models of sub-90nm NAND flash memory
cells, " in Proc. 8th Int. Conf. Solid-State
Integr. Circuit Technol., 2006, pp. 760-
762, doi: 10.1109/ICSICT.2006.306478.
[4] F. Masuoka, M. Asano, H. Iwahashi, T.
Komuro, and S. Tanaka, " A new flash
E2PROM cell using triple polysilicon technology, "
in Proc. Int. Electron Devices
Meeting, 1984, pp. 464-467, doi: 10.1109/
IEDM.1984.190752.
[5] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro,
and S. Tanaka, " A 256K Flash EEPROM
using triple polysilicon technology, "
in Proc. IEEE Int. Solid-State Circuits
Vt (a.u.)
(b)
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Bit Count (a.u.)

https://blogs.idc.com/2019/09/04/how-idcs-industry-cloudpath-saaspath-surveys-can-inform-your-cloud-saas-strategy https://blogs.idc.com/2019/09/04/how-idcs-industry-cloudpath-saaspath-surveys-can-inform-your-cloud-saas-strategy https://blogs.idc.com/2019/09/04/how-idcs-industry-cloudpath-saaspath-surveys-can-inform-your-cloud-saas-strategy https://blogs.idc.com/2019/09/04/how-idcs-industry-cloudpath-saaspath-surveys-can-inform-your-cloud-saas-strategy

IEEE Solid-States Circuits Magazine - Spring 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2022