IEEE Solid-States Circuits Magazine - Spring 2022 - 65

Conf., Dig. Tech. Papers, 1985, pp. 168-
169, doi: 10.1109/ISSCC.1985.1156798.
[6] M. Momodomi et al., " New device technologies
for 5 V-only 4 Mb EEPROM with
NAND structure cell, " in Proc. Tech. Dig.,
Int. Electron Devices Meeting, 1988, pp.
412-415, doi: 10.1109/IEDM.1988.32843.
[7] R. Shirota et al., " A 2.3 um2 memory cell
structure for 16 Mb NAND EEPROMs, " in Proc.
Int. Tech. Dig. Electron Devices, 1990, pp.
103-106, doi: 10.1109/IEDM.1990.237216.
[8] K.-D. Suh et al., " A 3.3 V 32 Mb NAND flash
memory with incremental step pulse programming
scheme, " in Proc. ISSCC '95 -
Int. Solid-State Circuits Conf., 1995, pp.
128-129, doi: 10.1109/ISSCC.1995.535460.
[9] T. Tanaka, M. Kato, T. Adachi, K. Ogura,
K. Kimura, and H. Kume, " High-speed programming
and program-verify methods
suitable for low-voltage flash memories, "
in Proc. IEEE Symp. VLSI Circuits, 1994, pp.
61-62, doi: 10.1109/VLSIC.1994.586214.
[10] K. Takeuchi, T. Tanaka, and T. Tanzawa, " A
multi-page cell architecture for high-speed
programming multi-level NAND flash memories, "
in Proc. Symp. VLSI Tech. Dig., 1997,
pp. 67-68, doi: 10.1109/VLSIC.1997.623810.
[11] J. D. Choi et al., " A 0.15um NAND flash
technology with 0.11um2
cell size for
1Gbit flash memory, " in Proc. IEDM, 2000,
pp. 767-770.
[12] T. Cho et al., " A 3.3 V 1 Gb multi-level NAND
flash memory with non-uniform threshold
voltage distribution, " in Proc. IEEE Int. Solid-State
Circuits Conf., Dig. Tech. Papers.
ISSCC (Cat. No. 01CH37177), 2001, pp. 28-
29, doi: 10.1109/ISSCC.2001.912417.
[13] L. Lee, C.-K. Lee, M.-W. Lee, H.-S. Kim,
K.-C. Park, and W.-S. Lee, " A new programming
disturbance phenomenon in
NAND flash memory by source/drain hotelectrons
generated by GIDL current, " in
Proc. 21st IEEE Non-volatile Semicond.
Memory Workshop, 2006, pp. 31-33, doi:
10.1109/.2006.1629481.
[14] N. Shibata et al., " A 70nm 16Gb 16-levelcell
NAND flash memory, " in Proc. IEEE
Symp. VLSI Circuits, 2007, pp. 190-191,
doi: 10.1109/VLSIC.2007.4342710.
[15] K. T. Park et al., " Zeroing cell-to-cell interference
page architecture with temporary LSB
storing and parallel MSB program scheme
for MLC NAND Flash memories, " IEEE J. Solid-State
Circuits, vol. 43, no. 4, pp. 919-928,
Apr. 2008, doi: 10.1109/JSSC.2008.917558.
[16] R. Cernea et al., " A 34MB/s-programthroughput
16Gb MLC NAND with all-bitline
architecture in 56nm, " in Proc. IEEE
Int. Solid-State Circuits Conf. - Dig. Tech.
Papers, 2008, pp. 420-624, doi: 10.1109/
ISSCC.2008.4523236.
[17] T. Futatsuyama et al., " A 113mm2 32Gb
3b/cell NAND flash memory, "
IEEE Int. Solid-State Circuits Conf. - Dig.
Tech. Papers, 2009, pp. 242-243, doi:
10.1109/ISSCC.2009.4977398.
[18] K. Prall and K. Parat, " 25nm 64Gb MLC
NAND technology and scaling challenges
invited paper, " in Proc. Int. Electron Devices
Meeting, 2010, pp. 5.2.1-5.2.4, doi:
10.1109/IEDM.2010.5703300.
[19] K. T. Park et al., " A 7MB/s 64Gb 3-bit/cell
DDR NAND flash memory in 20nm-node
technology, " in Proc. IEEE Int. Solid-State
Circuits Conf., 2011, pp. 212-213, doi:
10.1109/ISSCC.2011.5746287.
[20] C. H. Lee et al., " Channel Coupling phenomenon
as scaling barrier of NAND flash
memory beyond 20nm node, " in Proc. 5th
IEEE Int. Memory Workshop, 2013, pp.
72-75, doi: 10.1109/IMW.2013.6582101.
[21] J. Seo et al., " Highly reliable M1X MLC
NAND flash memory cell with novel active
in Proc.
air-gap and p+ poly process integration
technologies, " in Proc. IEEE Int. Electron
Devices Meeting, 2013, pp. 3.6.1-3.6.4,
doi: 10.1109/IEDM.2013.6724554.
[22] M. Helm, " 128Gb MLC NAND-Flash device
using 16nm planar cell, " in Proc. IEEE Int.
Solid- State Circuits Conf. (ISSCC), 2014, pp.
326-327, doi: 10.1109/ISSCC.2014.6757454.
[23] W. Jeong et al., " A 128 Gb 3b/cell V-NAND
flash memory with 1 Gb/s I/O rate, " IEEE J.
Solid-State Circuits, vol. 51, no. 1, pp. 204-212,
Jan. 2016, doi: 10.1109/JSSC.2015.2474117.
[24] S. Y. Yoon et al., " Programming method
for nonvolatile memory device, " U.S. Patent
8 902 666, Dec. 2, 2014.
[25] S. Morley et al., " Data balancing scheme
in solid state storage devices, " U.S. Patent
6 549 446, Apr. 15, 2003.
[26] H. G. Kim et al., " Nonvolatile memory
device and method of driving the same, "
U.S. Patent 8 325 517, Dec. 4, 2012.
[27] S.-M. Jung et al., " Three dimensionally
stacked NAND Flash memory technology
using stacking single crystal Si layers
on ILD and TANOS structure for beyond
30nm node, " in Proc. Int. Electron Devices
Meeting (IEDM '06), 2006, pp. 37-40,
doi: 10.1109/IEDM.2006.346902.
[28] H. Tanaka et al., " Bit cost scalable technology
with punch and plug process for
ultra high density flash memory, " in Proc.
IEEE Symp. VLSI Technol., 2007, pp. 14-
15, doi: 10.1109/VLSIT.2007.4339708.
[29] J. Jang et al., " Vertical cell array using
TCAT (Terabit Cell Array Transistor) technology
for ultra high density NAND flash
memory, " in Proc. IEEE Symp. VLSI Technol.,
2009, pp. 192-193.
[30] H. T. Lue et al., " A highly scalable 8-layer
3D vertical-gate (VG) TFT NAND flash
using junction-free buried channel BESONOS
device, " in Proc. IEEE Symp. VLSI
Technol., 2010, pp. 131-132, doi: 10.1109/
VLSIT.2010.5556199.
[31] J. Elliott and E. S. Jung, " Ushering in the 3D
memory era with V-NAND, " in Proc. Flash
Memory Summit Special Keynote B, Aug. 2013.
[32] K. T. Park et al., " Three-dimensional
128Gb MLC vertical NAND flash-memory
with 24-WL stacked layers and 50MB/s
high-speed programming, " in Proc. IEEE
Int. Solid-State Circuits Conf. Dig. Tech.
Papers (ISSCC), 2014, pp. 334-335, doi:
10.1109/ISSCC.2014.6757458.
[33] J. Lee, J. Jang, J. Lim, Y. G. Shin, K. Lee,
and E. Jung, " A new ruler on the storage
market: 3D-NAND flash for high-density
memory and its technology evolutions
and challenges on the future, " in
Proc. IEEE Int. Electron Devices Meeting
(IEDM), 2016, pp. 11.2.1-11.2.4, doi:
10.1109/IEDM.2016.7838394.
[34] H. Kim, S.-J. Ahn, Y. G. Shin, K. Lee, and
E. Jung, " Evolution of NAND flash memory:
From 2D to 3D as a storage market
leader, " in Proc. IEEE Int. Memory Workshop
(IMW), 2017, pp. 1-4, doi: 10.1109/
IMW.2017.7939081.
[35] D. Kang et al., " 256Gb 3b/cell V-NAND
flash memory with 48 stacked WL layers, "
in Proc. IEEE Int. Solid-State Circuits
Conf. (ISSCC), 2016, pp. 130-131, doi:
10.1109/ISSCC.2016.7417941.
[36] C. Kim et al., " A 512-Gb 3-b/Cell 64stacked
WL 3-D-NAND flash memory, "
IEEE J. Solid-State Circuits, vol. 53, no.
1, pp. 124-133, Jan. 2018, doi: 10.1109/
JSSC.2017.2731813.
[37] H. Maejima et al., " A 512Gb 3b/Cell 3D
flash memory on a 96-word-line-layer
technology, " in Proc. IEEE Int. Solid-State
Circuits Conf. (ISSCC), 2018, pp. 336-338,
doi: 10.1109/ISSCC.2018.8310321.
[38] S. Lee et al., " A 1Tb 4b/cell 64-stackedWL
3D NAND flash memory with 12MB/s
program throughput, " in Proc.
IEEE
Int. Solid-State Circuits Conf. (ISSCC),
2018, pp. 340-342, doi: 10.1109/ISSCC.
2018.8310323.
[39] D. Kang et al., " A 512Gb 3-bit/cell 3D 6thgeneration
V-NAND flash memory with
82MB/s write throughput and 1.2Gb/s interface, "
in Proc. IEEE Int. Solid- State Circuits
Conf. (ISSCC), 2019, pp. 216-218, doi:
10.1109/ISSCC.2019.8662493.
[40] D.-H. Kim et al., " A 1Tb 4b/cell NAND
flash memory with tPROG=2ms, tR=110µs
and 1.2Gb/s high-speed IO rate, " in Proc.
IEEE Int. Solid-State Circuits Conf. (ISSCC),
2020, pp. 218-220, doi: 10.1109/
ISSCC19947.2020.9063053.
[41] A. Khakifirooz et al., " A 1Tb 4b/Cell
144-tier floating-gate 3D-NAND flash
memory with 40MB/s program throughput
and 13.8Gb/mm2 bit density, " in
Proc. IEEE Int. Solid-State Circuits Conf.
(ISSCC), 2021, pp. 424-426, doi: 10.1109/
ISSCC42613.2021.9365777.
[42] J. Cho et al., " A 512Gb 3b/cell 7th-generation
3D-NAND flash memory with
184MB/s write throughput and 2.0Gb/s
interface, " in Proc. IEEE Int. Solid-State
Circuits Conf., 2021, pp. 426-428, doi:
10.1109/ISSCC42613.2021.9366054.
[43] M. Fujiwara et al., " 3D semicircular flash
memory cell: Novel split-gate technology
to boost bit density, " in Proc. IEEE
Int. Electron Devices Meeting (IEDM),
2019, pp. 28.1.1-28.1.4, doi: 10.1109/
IEDM19573.2019.8993673.
[44] C. W. Yoon, " Trend, hurdle, and core
technology for next generation high performance
storage system, " in Proc. IEEE
Asian Solid-State Circuits Conf., 2021.
[45] R. Fackenthal et al., " A 16Gb ReRAM with
200MB/s write and 1GB/s read in 27nm
technology, " in Proc. IEEE Int. SolidState
Circuits Conf. Dig. Tech. Papers
(ISSCC), 2014, pp. 338-339, doi: 10.1109/
ISSCC.2014.6757460.
[46] Y. Choi et al., " A 20nm 1.8V 8Gb PRAM
with 40MB/s program bandwidth, "
in Proc. IEEE Int. Solid-State Circuits
Conf., 2012, pp. 46-48, doi: 10.1109/ISSCC.
2012.6176872.
About the Author
Chi-Weon Yoon (chiweon.yoon@
samsung.com) received his M.S. and
Ph.D. degrees in electrical engineering
from the Korea Advanced Institute of Science
and Technology (KAIST), Daejeon,
South Korea, in 1999 and 2004, respectively.
He is a vice president of technology
with Samsung Electronics, Hwasung city,
18448, South Korea, where he has worked
for more than 16 years on the Flash Memory
Design Team. He holds more than 110
global patents on nonvolatile, memoryrelated
circuits and cell-operation algorithms.
His current research interests
include the design of high-performance
and low-cost cell-operation algorithms,
analog circuits, and high-speed, input-
output circuits.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2022
65
IEEE Solid-States Circuits Magazine - Spring 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2022
