IEEE Solid-States Circuits Magazine - Spring 2022 - 7

THE ANALOG MIND
Behzad Razavi
M
The Design of An LDO Regulator
Many mixed-signal systems incorporate
LDO regulators to generate local
supply voltages for various building
blocks. LDOs isolate the circuits from
one another's noise and from the
noise on the global supply,
V .DD For
optimum performance, the design of
each LDO is tailored to the particular
cell that it feeds. For example, an
LDO developed for a flash analog-todigital
converter is quite different
from one serving a VCO.
In this article, we design an LDO
for a 5-GHz LC VCO and target the
following specifications:
■ Input voltage: 1.2 V
■ Output voltage: 1 V
■ Maximum output current: 5 mA
■ Power supply rejection> 40 dB up
to 10 MHz
■ Output noise voltage150 /nV Hz
at 1 MHz.
The PSRR and tolerable output
noise are chosen according to the
VCO's supply sensitivity. We elaborate
on these points in the next section.
We also target a maximum LDO power
consumption of 1 mW beyond the
51 .26mA VmW
#
=
T 75 Cc=
that it provides
to the load. The design is carried out
in the slow-slow corner of 28-nm technology
at
. The reader is
referred to the LDO literature for background
information [1]-[5].
LDO/VCO Interface
We wish to regulate the supply voltage
of a 5-GHz VCO that operates
Vcont
Digital Object Identifier 10.1109/MSSC.2022.3167308
Date of current version: 25 June 2022
FIGURE 1: A VCO circuit fed by an LDO.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2022
7
B1
M1
Mv1
IVCO
XY
M2
Mv2
B2
and B ,2
within a PLL. We assume the VCO
is designed for a phase noise of
-110 dBc/Hz at a 1-MHz offset and
must incur no more than 1 dB of
noise penalty due to the LDO. The
VCO implementation is shown in
Figure 1, along with the LDO. The former
employs two capacitor banks,
B1
MOS varactors, MV1 and M ,V2
for digital tuning, and
for
analog control. As phase-noise optimization
dictates a PLL bandwidth
of no more than a few megahertz,
the VCO gain,
K ,VCO should typically
250MHz V
r
have approxinot
exceed (/ ). Noting
that low-frequency perturbations
on Vout
and Vcont
mately the same effect on the VCO
output phase, we express the phase
noise due to the LDO random noise,
,
S ,V LDO
as
Sf
z =
()
nV,22
2
K
VCO
4r f
VDD
LDO
L1
Vout
L1
S
LDO
,
(1)
where f denotes the frequency offset
from the carrier. At a 1-MHz offset,
this value must be sufficiently
below −110 dBc/Hz so as to introduce
only 1 dB of penalty. That is,
we must have
K
10 log
2
VCO
4r f
22 V,LDO +10-11010
/
S
10-11010
at f 1MHz=
/
= 1dB
(2)
. It follows that S ,V LDO
32 /.nV Hz
The PSRR is defined as
#
;;
VV /outDD
in Figure 1 and must remain less
than −40 dB. The −40-dB requirement
translates to two assumptions
as to how " clean " VDD
should be.
First, its random noise must be less
than
periodic perturbation on VDD
10 /.032nVHz Second, any
must
#
be so small that, with 40 dB of attenuation,
it introduces sufficiently low
spur levels at the VCO output. If we
IEEE Solid-States Circuits Magazine - Spring 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2022
