IEEE Solid-States Circuits Magazine - Spring 2022 - 70

From
DMA
Transmit
Packet
Assembler
Gaussian Filter
LUT
VCO_MOD
Receive
AGC
Envelope Det.
To
DMA Packet
Disassembler
CDR
>
Envelope Det.
Bandpass (F2)
AGC
Image Rejection
Hilbert Filter
ADC_Q
Gain_Q
Bandpass (F1)
GAIN_I
ADC_I
FIGURE 8: The RF baseband block diagram. Det.: detector; LUT: lookup table.
and includes the BLE modem as well
as modulation and demodulation DSP.
It further contains link-layer components
such as packet recovery, cyclic
redundancy checks, and data whitening.
A block diagram of the baseband
processor is pictured in Figure 8.
The BTLE analog transceiver is
shown in Figure 9, with its transmit
pad at the top left and receive pad at
the bottom left. An on-die PLL, shown
in Figure 10, generates its LO from a
2-MHz reference. The BTLE transmitter
uses a direct modulation architecture,
using the GFSK tune input to the PLL to
directly frequency-shift the LC oscillator
pictured in Figure 11. The BTLE
receiver uses a low-IF architecture,
featuring the passive mixer shown in
Figure 12, a programmable gain amplifier,
and bandpass filters. All were
designed from scratch, as were the
VCO, the PLL, and a pre-PA. Schedule
constraints forced the SoC to omit several
features that would be desired to
be integrated in commercial BLE transceivers,
including a PA, matching networks,
and a transmit-receive switch.
These components are instead integrated
at the PCB level. The receiver
ADCs and peripheral test circuits were
supplied by the course staff.
FREQ_SEL
Divider
Splitter
PFD
GFSK_OUT
In contrast to its digital designers,
the course's analog designers found
little to reuse. Process technology disclosure
requirements typically prevent
the publication of analog designs on resources
such as GitHub; these designs
must instead be walled off per institution.
The TSMC 28HPC technology had
not been used by Berkeley researchers
prior to the course, rendering no such
in-house library available. (A similar
28-nm technology had been used extensively
by Berkeley researchers and
became the basis for several peripheral
circuits.)
ADC
I_DATA
ADC
GAIN_CTRL
Q_DATA
Recent Berkeley research has also
produced a suite of productivity software
for process-portable analog IC
design, centrally including the Berkeley
Analog Generator (BAG) [7] framework.
While BAG was deployed by the
course's instructors for the RF transceiver's
ADC, the remaining studentdesigned
RF circuits were designed
in an industry-standard environment,
using Cadence's Virtuoso design suite
and Mentor Graphics's physical verification
suite (Calibre LVS and DRC). The
student-designed analog layout highlighting
key building blocks is pictured
in Figure 13.
Power Management
FIGURE 9: BLE transceiver block diagram.
70
SPRING 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
The OsciBear SoC is powered by a single-cell-compatible
supply of between
1.2 and 1.5 V. On-die linear voltage
LO 0°
LO 90°
IEEE Solid-States Circuits Magazine - Spring 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2022
