IEEE Solid-States Circuits Magazine - Spring 2022 - 71

VCO
Charge Pump
VREF
REF CLK
PDF
Up
Down
C1
EN
R1
REF CLK -
C2
Coarse
Tune
5
GFSK
Tune
4
REF CLK +
÷ 2
CML Divider and
Quadrature
Generation
4
Quadrature
Signals
RF TX
2/3 Divider Cascade
÷ N
11 RF Channel
Control Word
FIGURE 10: The RF LO generation PLL.
regulators then convert this battery
voltage into two 900-mV supplies, one
each for the digital and analog subsystems.
Each identical regulator uses
the topology shown in Figure 14. The
regulator feedback is output compensated,
allowing arbitrarily high decoupling
capacitance, which is of particular
benefit to the digital subsystem. Each
regulator output is fed to a chip-level
pad, allowing for a large off-chip compensation
and decoupling capacitance
as well as for separate analog and digital
power measurements with the ondie
regulators disabled.
Verification
In a typical industrial SoC design process,
a large portion of the engineering
effort is dedicated to verification. Academic
research ICs tend to be completed
by smaller teams with more modest
validation efforts. The OsciBear effort
landed somewhere in between. No student
designer was tasked full time with
verification duty, but all were tasked
with contributing to the effort. Helpfully,
the design productivity suite
includes the infrastructure for compiling
and executing to a target Rocket
configuration. This proved especially
valuable for chip-level simulations executing
target software. The AES and
baseband subsystems featured more
targeted verification, aided by their designers'
co-designed Chisel verification
frameworks.
The RF transceiver began from the
spreadsheet-based modeling of a link
budget and performance targets. Coupled
with a target architecture, it then
deployed Verilog-A models of each major
transceiver subcomponent (the
VDD
mixer, VCO, and so on) before committing
to a detailed schematic and layout
design. The parameters of these simplified
analog models then served as
requirements for the performance of
each component, which could be readily
checked in simulation and review.
Integration testing between analog
and digital subsystems commonly
remains a challenging industry task.
IREF
LON
V Varactor
aractor
LOP
VSS
FIGURE 11: RF LO VCO.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2022
71

IEEE Solid-States Circuits Magazine - Spring 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2022

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IEEE Solid-States Circuits Magazine - Spring 2022 - Cover1
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