IEEE Solid-States Circuits Magazine - Spring 2022 - 74

proved essential for the student designers'
success.
Dislike: Overcommunicating
and Overmeeting
The course format included very little
traditional lecturing and was nearly
entirely dedicated to student-presented
updates in a design meeting style
format. Many students cited the volume
of these updates as complaints:
■ " [The] amount of logistics that went
into everything and the fact that basically
half of the time the lecture
was going to be a little irrelevant if
it focused on a different team working
on something orthogonal to
what you're working on. "
■ " [The] constant check-ins during
lecture. "
Again, we empathize. Academic
course projects typically include far
more individual contribution time
and far less communication time than
the OsciBear SoC effort. These design
meetings more patterned an industrial
design environment. (We note that the
total time dedicated to these sessions
was typically between 3 and 5 hours
per week, a paltry amount for many
industry designers.)
Moreover, a large and diverse project
such as an 18-designer mixedsignal
SoC has many widely varied
technical subprojects. Student designers
took varied levels of interest in
subsystems outside their own. Students
were recommended, though not
required, to attend each other's design
updates and provide feedback and
questions, particularly on subsystems
that interacted with their own designs.
Further, the focus of these sessions
changes substantially over a project's
timespan. The early stages focus
heavily on architectural design and
planning. Students focused on these
facets were heavily involved, while
students focused on later-stage content
featured less prominently. The
later stages more heavily feature physical
design and logical and physical
verification. These roles then essentially
exchanged. In an industrial setting,
these varying focuses would
often be performed by specialist
74
SPRING 2022
teams and pipelined among projects.
Academic research designers, in contrast,
specialize less and contribute
more outside their core interest areas.
Student designers were encouraged
to do the latter, with the acknowledgment
that they could only reasonably
dive into so many technical areas.
Overall Impressions and
Future Interest
Responses to " Overall, what did you
think of this style of course relative to
more typical ones? " included:
■ " I think the time requirement is a
lot higher. Perhaps being real clear
about this at the beginning would
help a lot of students. "
■ " I really enjoyed the freedom we
were afforded along with the openness
of the staff (professors and
great TAs!). It was great that we
were able to explore the design
process but had a lot of support
and expertise from the teaching
staff. . . . Overall, this was one of the
best classes I've taken at Berkeley,
and the stuff I learned will stay with
me forever during my career. "
■ " Best course I've taken at Berkeley! "
And in response to " Has it made you
more or less interested in doing more of
this as a job or field of research? "
■ " I think this has made me more interested
in doing this as a job, but
I also recognize how much effort
goes into it. "
■ " More interested! The design process
was very fun in my opinion,
as we had the opportunity to go
through each stage of the design
process and see our design come
to life: design $ implementation
$ unit verification $ integration
with SoC $ SoC verification.
I am interested in designing bigger
and more complex designs! "
As noted in their overall impressions,
we believe students worked
unusually hard at the tape-out course,
dedicating substantially more of their
time relative to more typical courses.
Nonetheless, their impressions of the
process were overwhelmingly positive.
Of the 11 survey respondents,
nine reported that the course had
IEEE SOLID-STATE CIRCUITS MAGAZINE
made them more likely to pursue further
work or research in the area. The
remaining two reported their interests
stayed " about the same. "
Enthusiasm for the tape-out-based
course clearly reached their student
peers. For the ongoing spring 2022
edition, the course's enrollment nearly
tripled to more than 50 students.
Acknowledgments
Designing a complex SoC takes a village.
Doing so in a university semester
with primarily first-time designers
takes an even larger one. The authors
offer particular thanks to:
■ our guest lecturers, Daniel Grubb
and James Dunn of UC Berkeley and
Simone Gambini of Apple
■ the patient and attentive researcher-authors
of all of UC Berkeley's
home-grown IP and design software,
particularly including Abraham
Gonzalez, Harrison Liew, and
Zhaokai Liu
■ Muse Semiconductor, for designing
and coordinating the academic multiproject
wafer
■ TSMC, for providing educational access
to the 28-nm HPC technology
■ financial support and design review
from our industry partners at
Apple, especially Jared Zerbe and
Ramesh Abhari.
However, most of all, we thank and
congratulate our 18 incredibly talented
and enthusiastic students: Kareem
Ahmad, Sherwin Afshar, Josh Alexander,
Dylan Brater, Cheng Cao, Daniel
Fan, Felicia Guo, Nayiri Krzysztofowicz,
Ryan Lund, Alex Moreno, Jeffrey
Ni, Jack son Paddock, Griffin Prechter,
Troy Sheldon, Shreesha Sreed hara, Anson
Tsai, Eric Wu, and Kerry Yu.
-Dan Fritchman Member, IEEE
-Aviral Pandey Member, IEEE
-Kris Pister
-Ali Niknejad Fellow, IEEE
-Borivoje Nikolic´ Fellow, IEEE
References
[1] D. C. Burnett, B. Kilberg, R. Zoll, O. Khan,
and K. S. J. Pister, " Tapeout class: Taking
students from schematic to silicon in one
semester, " in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS), 2018, pp. 1-5, doi: 10.1109/
ISCAS.2018.8351506.
[2] J. Bachrach et al., " Chisel: Constructing hardware
in a Scala embedded language, " in Proc.
IEEE Solid-States Circuits Magazine - Spring 2022

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