IEEE Solid-States Circuits Magazine - Spring 2022 - 8

approximate the VDD
Vt ,
cos
perturbation
by mm~ the normalized spur
level is equal to ./()KV0012mmVCO
at an offset frequency of ~m . For
~
example, a spur level 60 dB below
the carrier at ()
requires that Vm be less than 40 mV
if (/ ).
~rm 210MHz
=
K 250MHz V
VCO r=
General Considerations
With a drop of only 200 mV from
VDD
to V ,out
For analysis and design of the LDO,
we wish to attach to its output a simplified
model of the VCO. Returning
to Figure 1, we observe that the LDO
provides a bias current equal to IVCO
and sees the two capacitor banks,
varactors, and common-mode (CM)
parasitics at X and Y. We then model
the VCO as depicted in Figure 2(b),
where CC CC22 2
VCOvar=+ +
B
C ,B C ,var and CCM
the LDO must employ
a pass transistor that acts as a current
source (rather than a source
follower) [5]. The basic topology
is displayed in Figure 2(a), where
operation amplifier (op amp) A1
regulates Vout
by adjusting the gate
,
=
voltage of M .0 For V 1Vout = we have
VR );RR1V 21 2=+ this is the
general case. If V 1VREF
able, we can omit R1 and R2
the op-amp input directly to V .out
REF () /(
is availand
tie
denote the bank,
varactor, and CM capacitances,
respectively. We assume I
and C ..O =VC 05pF
VC 5mA
O #
Pass Transistor Design
Transistor M0
in Figure 2(a) must
provide a maximum load current of
5 mA plus that which flows through
R1
;;= .,
and R .2 We should then select
(/ )WL 0 large enough so as to obtain
a reasonable VGS for this device. Specifically,
as VDS0 02V the transistor's
overdrive must not exceed this
value. For
lates to (/)/ .
0 $
n
resistance, r ,O0
;;.D0I 6mA , this transWL
10030mnm
As explained in [5], the coupling of
VDD
through this transistor's output
to Vout negligibly
CM and
affects the PSRR, allowing the minimum
length for this device. Such a
length is preferable as the capacitances
of M0
contribute to poles at
both P and X in Figure 2(a).
Op-Amp Requirements
The LDO's performance hinges upon
that of the op amp. The low-frequency
PSRR is given by
V
V
DD
out
. +cm (3)
1 ,
1
R
R
2
1
A1
where the loop gain is assumed
to be much greater than unity
[5] . If, for example,
have // .RR
A
V ., we
RE 09V
F =
110912
1 1000 9 110 41dB
=+=
and hence
/.
2 ./ for
PSRR 40dB.
As the LDO is to provide a rejection
VDD
M0
R1
P
A1
+
-
VREF
(a)
FIGURE 2: (a) A basic LDO topology and (b) the VCO model.
R2
(b)
VCO
IVCO
CVCO
X
Vout
VCO
of 40 dB up to 10 MHz, we conclude
that the op amp's open-loop 3-dB BW
must exceed this value. For a one-pole
design, therefore, the unity-gain BW
amounts to
1101011
= .
# MHzGHz.
It is interesting that a seemingly lowfrequency
LDO demands a fairly
wideband op amp. For this reason,
we prefer to use only thin-oxide (lowvoltage)
transistors in the op amp's
signal path.
The feedback loop consisting of the
A1
VDD = 1.2 V
M5
M3
Ra
Rb
M4
M6
AB P
M1
M2
Q
M7
W
L
25 µm
=
120 nm
Ra = Rb = 40 kΩ
FIGURE 3: A two-stage op amp used in the LDO.
8
SPRING 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
100 µA
ISS
M8
R2
M0
X
R1
IVCO
CVCO
Vout = 1 V
VCO
pass transistor and the op amp contains
several poles, possibly requiring
frequency compensation. The output
node in Figure 2(a) presents several
tradeoffs in this regard. First, if we
add capacitance to X so as to improve
the supply rejection at high frequencies,
the loop becomes less stable,
exhibiting peaking in the PSRR. Second,
if we reduce RR
12
raise the associated pole frequency,
power consumption climbs.
VCO example of interest here, CVCO
and ()
+ <
C
O = .
=
12 O 1k0
If ~ X
In the
RR rO12 0 appear to establish
an upper bound for the pole frequency
at X. For example,
and ()


IEEE Solid-States Circuits Magazine - Spring 2022
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