IEEE Solid-States Circuits Magazine - Spring 2023 - 13

-50
-40
-30
-20
-10
N = 32
106
N = 64
-160
-150
-140
-130
-120
-110
-100
107
Frequency (Hz)
(a)
108
109
104
N = 32
105
N = 64
106
107
Frequency (Hz)
(b)
FIGURE 23: (a) The input-output responses of third and fourth scaled loops and (b) corresponding PN profiles.
108
109
settling behavior of Figure 20(a)
and the output spectrum of Figure
20(b). The spur level is −52 dB, fairly
consistent with our conjecture that
it should remain constant.
Plotted in Figure 21 is
the input-output response,
displaying a BW of 103
MHz and suggesting that
it is not quite halved
with respect to the first
scaled loop. The peaking
is about 2.1 dB.
Figure 22 shows
Plotted in Figure 23(a) are the input-output
responses for the two
cases, yielding fBW
We can return
to the original
= 54 MHz and
26 MHz, respectively. We observe
that t he bandw idt h
i s scaled with realoop
bandwidth
calculations;
assume an SREF
dominated by the
CP and reduce fBW
accordingly.
the output PN with a plateau value
of −125 dBc/Hz . From (11), this
should be equal to −123 dBc/Hz because
N is doubled. The 2-dB discrepancy
may be avoided if the number
of sidebands in the pnoise analysis
is increased. Integrating this profile
yields a jitter of 47 fs, which is 15%
(rather than a factor of 2 ) greater
than that in the previous case.
Third and Fourth Scaled Loops
To form a clearer picture of the
trends, we study two more cases
with N = 32 and N = 64. For the former,
we select
C .162 pF, C 542
1 =
and fREF
=
2 =
fF,
= 937.5 MHz. For the latter,
1 =
we have C .324 pF, C 108 fF,
and fREF
= 468.75 MHz. According to
transient simulations, the output
spur level remains around −51 dB.
sonable accuracy. Figure
23(b) depicts the
output PN profiles and
suggests a plateau value
of −120 dBc/Hz for N = 32
and −113 dBc/Hz for N =
64. These results are fairly
aligned with SN,z CP ? 2
in (11). The integrated jitter values
amount to 60 fsrms
and 90 fsrms
, respectively.
The scaling of the jitter is
now somewhat close to the theoretical
factor of K .
Let us project the jitter of the
unscaled loop from our last case:
T /.90 300 64 195
D == We
may expect that the reference PN will
elevate this value considerably. However,
recall
j
fs#
fs
rms
from previous sections
that the input-referred CP contribution
is around −146 dBc/Hz, far exceeding
our presumed S
REF =-170 dBc/Hz.
Thus, the unscaled loop still exhibits
a jitter of about 200 fsrms
.
The jitter that we have obtained
is not minimum. We can return to
the original loop bandwidth calculations;
assume an SREF
the CP and reduce fBW
dominated by
accordingly.
References
[1] B. Razavi, " The design of a millimeterwave
VCO [The Analog Mind], " IEEE
Solid-State Circuits Mag., vol. 14, no. 3,
pp. 6-12, Summer 2022, doi: 10.1109/
MSSC.2022.3184443.
[2] B. Razavi, " The design of a millimeterwave
frequency divider [The Analog
Mind], " IEEE Solid-State Circuits Mag., vol.
14, no. 4, pp. 6-16, Fall 2022, doi: 10.1109/
MSSC.2022.3205805.
[3] D. Liao, Y. Zhang, F. F. Dai, Z. Chen, and
Y. Wang, " An mm-wave synthesizer with
robust
locking reference-sampling PLL
and wide-range injection-locked VCO, "
IEEE J. Solid-State Circuits, vol. 55, no. 3,
pp. 536-546, Mar. 2020, doi: 10.1109/
JSSC.2019.2959513.
[4] D. Yang et al., " A harmonic-mixing PLL
architecture for millimeter-wave application, "
IEEE J. Solid-State Circuits, vol. 57,
no. 12, pp. 3552-3566, Dec. 2022, doi:
10.1109/JSSC.2022.3209614.
[5] T. Sir iburanon et al ., " A low-power
low-noise mm-wave
subsampling
PLL
using dual-step-mixing ILFD and tailcoupling
quadrature injection-locked
oscillator for IEEE 802.11ad, " IEEE J.
Solid-State Circuits, vol. 51, no. 5, pp.
1246-1260, May 2016, doi: 10.1109/JSSC.
2016.2529004.
[6] A. Homayoun and B. Razavi, " Analysis
of phase noise in phase/frequency detectors, "
IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 60, no. 3, pp. 529-539, Mar.
2013, doi: 10.1109/TCSI.2012.2215792.
[7] B. Razavi, Design of CMOS Phase-Locked
Loops. Cambridge, U.K.: Cambridge Univ.
Press, 2020.
[8] C. S. Vaucher et al., " A family of low-power
truly modular programmable dividers
in standard 0.35-μm CMOS technology, "
IEEE J. Solid-State Circuits, vol. 35, no. 7,
pp. 1039-1045, Jul. 2000, doi: 10.1109/
4.848214.
The cost is a larger area occupied by
the capacitors.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2023
13
Input-Output Response (dB)
Output Phase Noise (dBc/Hz)
IEEE Solid-States Circuits Magazine - Spring 2023

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