IEEE Solid-States Circuits Magazine - Spring 2023 - 19

Any time you have a differential
load like this, you can add a crosscoupled
pair to amplify and latch the
output. So, this technique is easy to
add to your repertoire.
Open the Loop
Now let's look at something a bit less
obvious. Figure 1(b) is a block diagram
of a common function that you
might need: a monitor to check the
voltage of the power supply. This
straightforward implementation
features a resistor divider to measure
the supply, a voltage reference
to create a PVT insensitive threshold
point, and a comparator to render
an output. Pretty simple. But we're
about to make it even simpler.
First, consider what we might use
for a voltage reference. Figure 3(a) is
a popular low-voltage design, which
is described at length in another issue
of this magazine [3] (my secondfavorite
author). The details may
vary, but the choice of topology for
the voltage reference is not critical
to the discussion. Any bandgap core
that relies on feedback should work
for the example that follows.
The purpose of the amplifier in
Figure 3(a) is to drive the PMOS current
sources to the point at which nodes
A and B are at equal potential. When
that happens, the PMOS currents
have the perfect blend of positive and
negative temperature coefficients to
make a temperature-independent-
or at least insensitive-voltage in the
output resistor, Ro. (Of course, if the
resistors in the circuit have no temperature
coefficient, the current flowing
in Ro and all the PMOS transistors
is temperature independent, too.)
Let's refer to the current at this special
operating point as I0
.
OK, here's where we invoke the
magic. Open the feedback loop and
drive the circuit from the output by
turning M3 into a diode as shown in
Figure 3(b). Topologically, this is such
a minor change that you might miss
it if you weren't concentrating. But
opening the loop turns the voltage
reference into something else entirely.
You'll notice that the currents
in the PMOS devices in Figure 3(b)
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2023
19
now depend on the supply voltage.
At low supply, the currents will be
weak and possibly less than the reference
current,
I0, that we worked
so hard to generate in Figure 3(a).
When this happens, node A will be
at a higher voltage than node B. The
op-amp will be desperately trying to
pull the PMOS gates lower and deliver
more current. But its output has
been disconnected, so it just slams
into the negative rail (GND). Likewise,
if the supply voltage is high,
the PMOS currents will be greater
than the balance current, I0
, and the
op-amp output will be driven to the
positive rail (VDD). This is exactly
the function we were looking for
with Figure 1(b): a logic level signal
that indicates the state of the supply
voltage. There is no comparator; the
op-amp has assumed that role...for
now. (An open-loop op-amp is generally
not a satisfactory comparator.
See " Open-Loop Comparators. " )
Impressed? We're not even close
to being finished. The first thing we
need to fix is the supply detection.
With the circuit of Figure 3(b), the
currents in the PMOS devices are
dependent on the Vgs
of the diode
connected device, M3. Not good: we
cannot accurately predict what supply
voltage will trip the detector. We
(a)
(b)
FIGURE 3: From reference to sensor, it's a short trip! (a) The low-voltage reference from [3].
(b) Opening the loop and driving it from the output turns the block into a VDD monitor...but
not a good one.
OPEN-LOOP COMPARATORS
Don't! Bad idea! Comparators should always have regenerative positive feedback, either
clocked or always on in the form of hysteresis. Sure, high-gain amps look attractive, especially
if you don't have a clock available and you don't like having the two different thresholds that
result from hysteresis. Nevertheless, you should avoid them. If you just can't, then redefine the
problem so you can.
Without feedback, high-gain amps tend to have very low frequency poles. You have wait
a while to get the full accuracy that the dc gain implies. High-gain amps may also have long
recovery times from overload situations, which are a comparator's bread and butter. The whole
point of an unclocked comparator is to quickly respond to changing conditions without having
to wait for a clock edge, so a slow comparator is pointless.
By far, the most serious problem with open-loop comparators, however, is invalid logic levels
at the output. No matter how high the gain is, there is always some input voltage that will result
in an undefined logic state, a dc form of metastability, if you will. This can be a disaster, and
Murphy's Law pretty much guarantees it will happen. The most familiar mistake is to overestimate
the gain in simulation. Transistor output impedance, which is so essential for gain, is
not critical for logic circuits. Consequently, your transistor output impedance may be poorly
modeled, inadequately measured, or just not well controlled in the fab. Whatever the reason,
open-loop comparators-even in the hands of experts-can and do fail.
Beg to differ? Argue with me at shifobrains@ieee.org. I promise to be polite.

IEEE Solid-States Circuits Magazine - Spring 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2023