IEEE Solid-States Circuits Magazine - Spring 2023 - 65

fSW at IL = 1 mA
VHA = 18 V
VIN = 15.2 V (Ripple of 160 mV)
VOUT = 15 V
1 V
1.E-8
1.E-7
1.E-6
1.E-5
1.E-4
1.E-3
1.E-2
100
(a)
VIN
fSW at IL = 20 mA
IL = 20 mA
IL = 1 mA
VOUT
PSR = -75 dB
at 30 kHz
1k
10k
Frequency (Hz)
(b)
FIGURE 11: Measured results of the VIH LDO regulator: (a) time-domain waveforms and (b) noise spectral density [10].
boosted rpass (by the TC loop), considering
(3). It should also be noted
that the supply ripple on VHA can be
significantly rejected because of a
high rds,V by MV working in the deep
saturation region.
Figure 9 describes
the
mentation of
= b $
implethe
VIH LDO regulator,
designed for VIN = 15.2 V and
VOUT = 15 V. For the current regulation,
(),II
CV and IV must be
sensed and copied to IGU and IGD, respectively.
The IV is scaled down to
IVS via 5-V PMOS MVS, and the circuit
composed of laterally diffused MOS
Mn3−n4 and Mp3−p4 absorbs IVS and
mirrors it to IGD while protecting MVS
from the overvoltage stress. In virtue
of selecting a PMOS as the pass
transistor (MV), it becomes simpler
to sense IV via MVS because MV and
its counterpart MVS share the same
gate-to-source voltage. Otherwise,
if an NMOS is chosen as MV, a more
complicated circuit would be necessary
to detect IV. The P-type MV also
contributes to increasing the loop
gain of TV for better voltage regulation.
On the other hand, ICS, a scaled
replica of IC, is detected by voltage
feedback using an amplifier (A2)
and Mp2. This voltage feedback loop
makes the drain voltage of MCS equal
to that of MC, assisting in sensing IC
through MCS even when MC works in
the deep triode region. In this work,
the current gain of (/ )II
b CV
=
is designed
to be 200 A/A. To cope with
light load conditions, the current IBV
is also equipped, guaranteeing the
minimum IV, min (= 30IBV) preventing
the TV loop from turning off. The capacitor
CC and the series resistor RZ
are used for stability compensation.
Figure 10 shows the simulated PSR
of the VIH LDO regulator when VIN
= 15.2 V, VOUT = 15 V, and VDO = 200
mV (1.3% of VOUT). For various load (IL)
conditions ranging from 0 to 20 mA
(full load), the PSRs are simulated to
be better than −80 dB at 10 kHz.
Figure 11 gives the measurement
results of a VIH LDO regulator chip
fabricated in a 180-nm high-voltage
bipolar-CMOS-double-diffused-MOS
(BCD) process. Figure 11(a) demonstrates
the ripple suppression even
at ultra-LDO voltage of 200 mV (VIN =
15.2 V and VOUT = 15 V). As can be
seen, the noise is invisible at the LDO
output (VOUT) despite the high ripple
voltage (∆160 mV) at the LDO input
(VIN). Figure 11(b) details the noise
spectral density measured at VIN and
the regulated VOUT. It can be observed
that the VIH LDO regulator rejects
the ripple noise of VIN, with a PSR of
−75 dB at 30 kHz when ILoad = 20 mA.
The total output noise integrated
from 10 Hz to 0.5 MHz was measured
to be 23.6 μVrms (ILoad = 1 mA) and
28.7 μVrms (at ILoad = 20 mA), including
the ripples of VIN. It is worth noting
that such excellent low-noise and PSR
capabilities were obtained by consuming
an ultra-LDO voltage (only
1.3% of VOUT) by virtue of the VIH design.
The measured performance is
summarized in Table 2, demonstrating
that the energy-efficient (PCE =
98.6%) LDO regulator is feasible without
sacrificing its regulation performance
(high PSR).
Other Promising Approaches
Figure 12 illustrates various design
examples to realize energy-efficient LDO
regulators. As shown in Figure 12(a),
the digital LDO (D-LDO) regulator
[11] is an attractive option to minimize
the power loss because the
segmented pass transistors behave
like switches by operating in the
triode region, allowing a very LDO
voltage (VDO). In addition to the benefits
of its synthesizable and scalable
TABLE 2. THE MEASURED
PERFORMANCE AFTER PROTOTYPE
CHIP FABRICATION OF THE VIH
LDO REGULATOR [10].
VIH LDO REGULATOR
Technology
Die area
Input (VIN)
Output (VOUT)
Maximum
power
PCE (h)
Quiescent
current (IQ)
PSR
Output noise
180-nm high-voltage BCD
0.34 mm2
15.2 V
15 V (i.e., VDO = 200 mV)
300 mW
(Peak) 98.6%
16 nA at ILoad = 1 mA
−75 dB at VDO = 0.2 V
(1.3% of VOUT)
28.7 nVrms integrated in
10 Hz-0.5 MHz
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2023
65
100k
1M
Noise [V/sqrt(Hz)]
IEEE Solid-States Circuits Magazine - Spring 2023

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