IEEE Solid-States Circuits Magazine - Spring 2023 - 9

The Effect of Loop Scaling on Jitter
and Spurs
Our ultimate goal is to be able to
predict the performance of the
unscaled loop from that of the
scaled one. To this end, we construct
the PN profiles of the free-running
or phase-locked VCO for K = 1 and
K > 1, neglecting flicker noise upconversion
for simplicity. As illustrated
in Figure 9, the jitter falls for K > 1
and is expressed from (1) as
2
DTj =
4cm REFREF
()
K
N SKf
2r
= 1
K
4 2 2
NS fREF REF
2r
T
T
VCO
VCO
(9)
(10)
fREF
where the factor of four accounts
for only the VCO contribution. That
is, the VCO-induced output jitter of
the scaled loop is lower by a factor
of
K .
Additionally, the reference, the
PFD, and the CP also introduce PN,
which dominates the " in-band " components,
i.e., those between fREF
and +f .REF
-
Lumping these contributions
into SREF, we observe from
Figure 10 that the corresponding
jitter (the square root of the area
under the profile) falls by a factor of
K regardless of the shape of the
input-output transfer function. We
can then predict the output jitter as
we begin with a heavily scaled loop
and gradually decrease K.
The effect of loop scaling on the
output reference spurs is studied
as follows. Suppose a scaled PLL
exhibits a certain ripple amplitude,
Vr
VK
r VCOREFr4 f
)
if we approximate
the ripple by a sinusoid. We now
increase C1
K
N SREF
2
K > 1
-KfBW
. The output spur level is given by
/(
and C2 by a factor of K and
decrease the reference frequency by
the same factor. For a fixed PFD/CP
design, the ripple amplitude falls
by K, yielding a spur level equal to
(/ )/(/)/(
fREF
VKKf KV K44VCOREF
). That is, the spur level remains
rrVCO
rr=
constant. This point holds even if
the ripple is not sinusoidal.
The Choice of MMD Topology
Frequency synthesis requires an
MMD whose divide ratio can change
K
N SREF
2
K > 1
-KfBW
-fBW
+fBW
+KfBW
FIGURE 10: The effect of loop scaling on reference, PFD, and CP PN.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SPRING 2023
9
f
N2SREF
PN Due to REF
and PFD/CP
K = 1
-fBW
FIGURE 9: The effect of loop scaling on VCO PN.
+fBW
+KfBW
f
N2SREF
Phase−Locked
VCO PN
Sφ(f)
Free−Running
VCO PN
K = 1
FIGURE 8: The scaling of the loop parameter values.
IP
CP
R1
C1
N
KVCO
VCO
C2
fout
in unity steps. Popular MMD topologies
include the pulse-swallow counter
and Vaucher's structure [8]. Used
for our millimeter-wave
design [1], the latter also
lends itself to loop scaling
much more easily. This is
due to its modular form.
As shown in Figure 11,
we can cascade two or
more stages so as to
scale N by a factor of
K. The pulse-swallow counter, on
the other hand, would need to be
redesigned for different K values if
its complexity must be minimized.
Our ultimate
goal is to be able
to predict the
performance of
the unscaled loop
from that of the
scaled one.
Simulation Procedure
We perform three simulations
for each choice
of K so as to quantify the
synthesizer's behavior.
First, we run a transient
simulation and examine
1) the VCO control settling
time and 2) the reference
spurs in the output spectrum. We
also consider the time alignment of
IP
KfREF
CP
R1
C1
K
K
N
KVCO
VCO
C2
K
fout
IEEE Solid-States Circuits Magazine - Spring 2023

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