IEEE Solid-States Circuits Magazine - Summer 2019 - 14

a =2

C - Cp
,
C + Cp

employs a variant of such a network
a nd ca librates the ef fect of the
pa rasitic capacitances. As shown
in Figure 10, this is accomplished
by adding
1) a programmable capacitor, C B, to
each node that absorbs C p and
reaches C/2 after calibration
2) a section consisting of C and C cal
that injects or removes charge
from the array.
During calibration, a known voltage
is applied to the ADC input, and Vcal
is adjusted to obtain the correct digital output [8].
A n ot h e r appl ic at io n of C-2C
ladders aims for high-frequency
resolution in digitally controlled oscillators (DCOs) [9]. A critical issue
affecting the output jitter of digital
phase-locked loops, the DCO output
frequency steps must often be less
than 1 part per million with respect
to the oscillation frequency itself.
Such fine steps demand extremely
small unit capacitors in the tuning
network of IC DCOs. To avoid dealing
with the parasitics and modeling
issues related to very small geometries, we seek methods that attenuate the effect of a capacitor.
The DCO in [9] is realized as shown
in Figure  11, where tuning elements

(13)

and
a . 2c 1 -

Cp 2
m,
C

(14)

if C p % C. A solution exists, but a
must be slightly less than two, an
undesirable condition because it
is difficult to subtract a certain
amount from a capacitor. In our final trial, we assign a capacitance of
aC to the branches while keeping
the rightmost capacitor equal to bC
[Figure 9(c)]. Now, the conditions
emerge as
b =2

(15)

aC = C + C p .

(16)

and

That is, the branch capacitors must
be raised by a value equal to C p . Although C p is not precisely defined,
an approximation thereof can be
added to the unit C, thus providing
partial correction and lowering the
DAC nonlinearity.
Owing to its compact nature, the
C-2C ladder has found a wide range
of applications. In [8], a 7-b successive approximation register (SAR)
analog-to-digital converter (ADC)

2TC and TC are added to each section and controlled by 2 b. Let us begin with the rightmost section and
denote the programmable component
by kTC, where k = 0, 1, 2, or 3. Thus,
C eq =

2C (2C + kTC )
2C + 2C + kTC

(17)

and
C eq . C + k TC,
2

(18)

where kTC in the denominator is
neglected. Continuing the recursion,
we observe that each section presents at its input three components:
one equal to C, one equal to half its
own programmable capacitance, and
one equal to half the total programmable capacitance presented by the
section to its right. In other words,
the capacitance loading the oscillator can be expressed as
k TC
C in = C + k 1 TC + k 2 TC + 3
+ g,
2
4
8
(19)
where k j TC denotes the value of the
programmable capacitance in section j. This result suggests that the
effect of TC can be reduced arbitrarily if the capacitor is placed deep
in the cascade. Indeed, the DCO in
[9] employs 14 sections to achieve a
remarkable frequency resolution of
4 Hz at 60 GHz.

Switch Network

Ccal

2C

CB
C

2C

Answers to Last Issue's Questions

CB
C

SAR Logic

CB
C

CB
C

C

2C

Switch Network

Vcal

FIGURE 10: A SAR ADC using a variant of the C-2C ladder.

Section 1
2C
C

Vin

Section 2
2C

2∆C

∆C

D1

D2

C

SU M M E R 2 0 19

Vout

M1

2C
2∆C

C

∆C

R1
2∆C

∆C

C

+
A1
-

X
VREF

CM R
L Load

R2

Ceq

FIGURE 11: A DCO using a C-2C ladder for fine frequency control.

14

1) How does C M shape the powersupply rejection ratio (PSRR) of
the circuit in Figure 12?
L et us assume that the op
amp has a one-pole response
equal to A 0 / (1 + s/~ 0) and the
small-signal resistance, R L, is
much less than R 1 + R 2 . We open

IEEE SOLID-STATE CIRCUITS MAGAZINE

FIGURE 12: The use of a smoothing capacitor to absorb load transient currents.
IEEE Solid-States Circuits Magazine - Summer 2019

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