IEEE Solid-States Circuits Magazine - Summer 2019 - 17
As the comparator input becomes
arbitrarily small, its regeneration time
becomes arbitrarily large. However,
during how many bit cycles can the
comparator input actually become
arbitrarily small? The answer is only
one of them. During successive approximation, the input signal is tested
against B DAC voltages, but it can reside within !0.5 least significant bits
(LSBs) of at most one DAC voltage. This
is often called the hard decision, because it can cause an arbitrarily long
regeneration time. All other decisions
are easy, in the sense that regeneration happens quickly for comparator
inputs with magnitude greater than
0.5 LSBs. In designing the synchronous SAR ADC, we must set the value
of N assuming that any decision could
be the hard decision. This is, in fact,
quite wasteful, because, in all bit cycles but one, the time available for regeneration is overprovisioned. Rather
than waiting through a full TCLK, it
would be more efficient to proceed
from one bit cycle to the next immediately after the regeneration and fixed
delays have elapsed. This is the basis
for the asynchronous architecture.
Figure 1(a) shows a block diagram
of the asynchronous architecture,
and Figure 1(b) compares its timing
to that of its synchronous cousin.
The main implementation difference
is in the SAR logic, which must now
detect when the comparator resolves,
capture its output, switch the DAC,
reset the comparator, and kick off the
next decision, all without relying on
an externally applied clock. In a real
implementation, DAC settling and
comparator reset happen concurrently. The longer of these two delays
determines the timing, which we simply refer to as TFIX, the regenerationindependent delay in the SAR loop.
In the synchronous architecture,
we allocate the same timing margin
for metastability in each bit cycle,
color-coded as red in Figure 1(b). If
φs
VID
-
VDAC
DAC
Capture Latch
+
D
Vod
∑
Out
L
Vres
φc
Pulse
Generator
(a)
Ts
φs
T Track and Hold
φc
Synchronous
T
CL D
M
CL D
M
CL D
M
C L D M
C L D M
C LD M
D3
D2
D1
C
L M
Comparator
C Decision
L Capture Latch
D6
D5
D4
D0
φc
Asynchronous
D DAC Settling
R Clock Reset
T
Ttrack
C
R
R
R
R
R
C
C
C
C
L D L D
L D
L D
L D
D6
D5
TFIX
TFIX
treg,1
treg,2
D4
D3
D2
C
R
L D
D1
C
L
M
M Timing Margin
D0
TFIX
treg,6
treg,7
(b)
FIGURE 1: (a) An asynchronous SAR ADC block diagram. (b) A timing diagram comparison between the synchronous and asynchronous topologies. While a synchronous design allocates timing margin to each bit cycle individually, an asynchronous scheme allocates a single block
of timing margin for all bit cycles to share. vod: differential output voltage; D: decision.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SU M M E R 2 0 19
17
IEEE Solid-States Circuits Magazine - Summer 2019
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2019
Contents
IEEE Solid-States Circuits Magazine - Summer 2019 - Cover1
IEEE Solid-States Circuits Magazine - Summer 2019 - Cover2
IEEE Solid-States Circuits Magazine - Summer 2019 - Contents
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