IEEE Solid-States Circuits Magazine - Summer 2019 - 18

45
MSB
Second MSB
Third MSB

6b
7b
8b

40
∑treg,easy /t

vres /VFS

0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1
vID/VFS
(a)

9b
10 b

30
25
20
15

0.2 0.3 0.4 0.5

10
-0.5 -0.4 -0.3 -0.2 -0.1

0 0.1
vID/VFS
(b)

0.2 0.3

0.4

0.5

FIGURE 2: (a) A plot of residual voltage during the MSB, second MSB, and third MSB decisions as a function of ADC input voltage. Given the
input voltage, we know the residual voltage for every decision, and therefore we know the regeneration time. (b) The total regeneration time
of easy decisions as a function of ADC input voltage (solid) and average value (dashed).

a bit cycle doesn't use up its timing
margin (because the comparator input happens to be large), this time is
wasted. Similarly, if a bit cycle exhausts its timing margin (because
the comparator input happens to be
small), then a metastability error occurs. Timing margin cannot be borrowed from the subsequent bit cycle,
even though all other decisions are
guaranteed to be easy. In contrast,
the asynchronous architecture allocates a single block of timing margin
for metastability, which any individual bit cycle can use as needed. We
would expect that for a fixed metastability probability (Pmeta), we can
run the ADC faster, while for a fixed
speed, we can achieve a much lower

TABLE 1. THE TOTAL REGENERATION
TIME OF EASY DECISIONS AVERAGED
OVER FULL-SCALE RANGE FOR
6-14-B RESOLUTION.

Teasy /x

SU M M E R 2 0 19

Pmeta . How can we calculate Pmeta for
the asynchronous architecture?
We can answer this question by
finding the available regeneration
time for the hard decision, converting this to a range of residual voltages
(i.e., the comparator input) that cause
the hard decision to run out of time,
and then finding the probability that
the voltage lies in this range. To find
the available time, we consider the total regeneration time of the easy decisions. An easy decision must have a
residual voltage greater than 0.5 LSBs
in magnitude, so its regeneration
time must satisfy
t reg,easy 1 x ln

VDD
= x ln^2B + 1h .
f 1 VDD p
2 2B

While the total regeneration time of
all easy decisions cannot exceed B - 1
times the bound on the right-hand
side, this corresponds to the impossible scenario in which the comparator
input is 0.5 LSBs for every decision.
Figure 2(a) shows the residual voltage for the three most significant bit
(MSB) decisions as a function of the
ADC input v ID, which is all we need
to calculate a better estimate. We're
interested only in the total regeneration time of easy decisions, so, for
each decision, we ignore the range
of inputs v ID that would bring its residual voltage within !0.5 LSBs of
zero (corresponding to that particular decision being hard). Summing up

IEEE SOLID-STATE CIRCUITS MAGAZINE

the regeneration times, we obtain the
plot in Figure 2(b), which shows the
total regeneration time of easy decisions as a function of v ID for several
ADC resolutions.
At this point, we invoke the assumption that the ADC input v ID is
uniformly distributed across the fullscale range. This key assumption of
the article is applied to the derivations and results that follow. However, for any reasonably well-behaved
input signal distribution, we expect
similar results. The dashed lines in
Figure 2(b) represent the average
value of the total regeneration time
of all the easy decisions, which we
denote as Teasy /x in our subsequent
analysis. Interestingly, Teasy /x can
be hand-calculated (see "Calculating
Teasy "), giving the values summarized in Table 1.
The conversion period of the ADC,
T s, must be long enough to accommodate the track-and-hold interval
Ttrack, B - 1 fixed delays, Teasy, and
the regeneration time of the hard
decision t reg,hard . If the regeneration
time of the hard decision exceeds the
time allocated to it,
t reg,hard 2 Ts - Ttrack - (B - 1) TFIX - Teasy,
then a metastability error occurs. Let us
now write the timing parameter N in a
way that works for both synchronous and
asynchronous approaches, by replacing
TCLK - TFIX from the synchronous case

IEEE Solid-States Circuits Magazine - Summer 2019

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