IEEE Solid-States Circuits Magazine - Summer 2019 - 20

The asynchronous architecture allocates a single
block of timing margin for metastability, which
any individual bit cycle can use as needed.

deterministic, i.e., it excludes comparator input-referred thermal noise.
We then augment this model to include the effects of comparator noise.

Metastability Code Error
Distribution With Random Input
Signal and Noiseless Comparator
In the absence of noise, the ADC input v ID determines the entire timing of the asynchronous SAR ADC.
We invoked similar reasoning in
the previous section, when we used
Figure 2 to add up the regeneration
times of easy decisions for all inputs
across the full-scale range. Given
v ID, we can calculate the DAC voltage in each bit cycle. It's just a matter of how long each bit cycle takes
and whether there's time to finish all
cycles before the end of the conversion period T s . How long the ith bit
cycle takes is determined by the residual voltage v res, i = v DAC, i - v ID, the
difference between the DAC voltage
(determined by v ID) and v ID itself.
Given v ID, we can calculate how long
the comparator spends regenerating each decision. Between the end
of one decision and the beginning
of the next, there is the fixed delay
TFIX . We can draw a timing diagram
showing the self-timed comparator
enable signal as well as the comparator output voltage, all based strictly
on knowledge of the ADC input v ID .
An example is constructed in Figure 4(a), where v ID resides very close
to the bottom of the input range that
maps to the code 101.
Let's walk through the timing
diagram in Figure  4(a) step by step.
During the track interval (z S), the
sampling signal is asserted, and the
ADC output code is reset (to 000 in
this example). Immediately following
the track interval, the comparator
enable signal (z C) is asserted, beginning the regeneration time for the

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SU M M E R 2 0 19

MSB decision. During this time, the
comparator output is in a metastable
state, denoted as X. The ADC output
code is X00. Then, the comparator
finishes regenerating a logic 1. Immediately following regeneration, the
comparator is reset, and the fixed delay begins. In the course of this time,
the ADC output code is 100. At the
end of the fixed delay, the comparator enable signal is asserted again,
beginning the regeneration time for
the second MSB decision. The ADC
output code is now 1X0. The comparator soon resolves a logic 0, the ADC
output code switches to 100, and another fixed delay begins. Finally, the
comparator enable signal is asserted
for the LSB decision, and the ADC
output code switches to 10X. Notice,
though, that the comparator does not
resolve the LSB decision by the end of
the conversion period. A metastability error is born.
Now imagine that v ID is not close
enough to the 100-101 transition level
to cause a metastability error but instead resides right in the middle
of the code 101. We can use the dark
red, dark green, and blue timing
bands in Figure 4(a) to find out what
happens to the regeneration times of
the MSB, second MSB, and LSB decisions, respectively. Recall that, given
v ID, all regeneration times are determined. The widths of the dark timing bands represent the regeneration
times, and those of the light timing
bands represent the fixed delays (notice how the fixed delay widths are
constant). If v ID moves from the bottom to the middle of code 101, the
MSB regeneration time decreases,
the second MSB regeneration time
increases, and the LSB regeneration
time decreases significantly. Now
there's enough time for the comparator to resolve the LSB decision before
the end of the conversion period.

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The timing bands can, of course,
be extended from code 101 to the
entire full-scale range, depicted in
Figure 4(b). It's just important to remember that the ADC output code
inside each band is different. For example, in code 010, the timing bands
would instead be labeled (left to right)
000, X00, 000, 0X0, 010, 01X, and finally 010, the ideal ADC output code.
We now have a graphical way to find
the ADC output code given v ID at any
instant in time. There is one instant
in time of particular importance, and
that is when the conversion ends. In
the first example (v ID very close to
the bottom of code 101), the ADC output code at the end of conversion is
10X. Now, all we need to do is decide
how to treat the X, and we will know
the ADC output code error caused by
this metastable event.
Following [4] and Part I of this tutorial, we assume that the capture
latch output switches in an abrupt
but delayed jump. In other words, we
assume that the capture latch output
stays in its reset state until regeneration is over, at which time it switches
instantaneously to the correct value.
Under this assumption, X can be replaced by 0 in the ADC output codes
of Figure 4(a): 000, 000, 100, 100,
100, 100, 101. With v ID very close to
the bottom of code 101 and insufficient time to resolve the LSB decision, the ADC output code at the end
of conversion is 100, and the code error is −1.
The method of timing bands gives
us a function from v ID to the ADC output code error. How can we use this
to find the code error PMF? Imagine
drawing a vertical line on Figure 4(b),
exactly at time T s, the end of conversion. Figure  4(c) plots the 1D cross
section of the bands at this time. Here,
we can easily see the ranges of v ID that
cause the conversion to terminate during the MSB regeneration (dark red),
first fixed delay (light red), second
MSB regeneration (dark green), second fixed delay (light green), and so
on. The regions that are not distinctly
colored correspond to the conversion
terminating after all decisions have
IEEE Solid-States Circuits Magazine - Summer 2019

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