IEEE Solid-States Circuits Magazine - Summer 2019 - 30

noise level to cover the range between
ENOB = 7 (noiseless) and ENOB = 4.
Additionally, we sweep the timing
parameter N from −4 to 7 and plot
the resulting BER estimate against
(Ts - Ttrack)/x, the analog-to-digital
conversion time without the input
tracking interval. These plots give us

a feel for how fast we can run the ADC
before we encounter metastability
troubles. For large analog-to-digital
conversion times, we see that both
the fast (red) and slow (blue) designs
converge to the same BER at ENOB of
4 and 5. These horizontal asymptotes
are set purely by thermal noise and

TFIX/τ = 8

100

TFIX/τ = 16

10-5

BER

ENOB = 4-7
10-10

10-15

10-20

80
100
(Ts - Ttrack)/τ

120

140

FIGURE 15: A plot of BER estimate versus (TS - Ttrack)/x (analog-to-digital conversion time
without input tracking interval). Plots are for 7-b ADCs, with small fixed delay (TFIX /x = 8) in
blue and large fixed delay (TFIX /x =16) in red. For both cases, the ADC's thermal noise level
is varied to cover the range between ENOB = 7 (noiseless) and ENOB = 4. The timing parameter N is swept from - 4 to 7.

TFIX/τ = 16

TFIX/τ = 8

100

4 LSBs

8 LSBs

Error Rate

10-5

10-10
8 LSBs

4 LSBs

10-15

10-20

80
100
(Ts - Ttrack)/τ

120

140

FIGURE 16: A plot of the rates of metastable events errors with magnitudes of $ 4 and $ 8
LSBs, for large fixed delay (blue) and small fixed delay (red). The data from Figure 15 are
overlaid in gray. The x- axis (TS - Ttrack)/x represents the analog-to-digital conversion time
without the input tracking interval.

SU M M E R 2 0 19

IEEE SOLID-STATE CIRCUITS MAGAZINE

are unrelated to metastability behavior. As we go farther to the left (i.e.,
as we stress the ADC with a shorter
conversion time), we run into steep
BER asymptotes set by the combined
effect of noise and metastability.
While the previously discussed
plot is very useful for design validation, producing it is labor intensive
and requires detailed system knowledge, including the exact channel
model. Is there a shortcut that lets
us obtain reasonable estimates more
quickly? Indeed, we can rely on some
intuition gained from the PMF characteristics seen in Figure 11. In an asynchronous design, metastability errors
of large magnitude are extremely rare
and will not significantly impair the
BER. Additionally, small errors on the
order of 1-2 LSBs are hard to distinguish from thermal noise and will
therefore not lead to dramatic shifts
in the horizontal BER asymptotes. Ultimately, what should matter most are
metastability errors with magnitudes
of about 4 or 8 LSBs. In Figure 16, we
plot the rates at which pre-FFE errors
≥ 4 LSBs and ≥ 8 LSBs occur for both
the slow and fast designs and with the
plots from Figure 15 overlaid in gray.
We observe that the 8-LSB error rate
essentially coincides with the BER of
the noiseless design and, hence, constitutes a useful and easy-to-construct
asymptote without knowing the specifics of the FFE. As a more conservative option, the 4-LSB curve could be
considered.
Fig ure 17 shows how this approach can be used to get a quick
feel for the maximum possible ADC
speed. Given a certain target BER
(e.g., 10-6 or 10-12), we can look for
the intersections that define the possible operating ranges (marked in
green). Note that the ADC can run
only slightly faster for the higher BER
target. Lastly, it is interesting to consider the overlaid Pmeta curves, which
are the probability of any metastable
event in the ADC. Clearly, designing with this pessimist metric would
leave a significant amount of performance on the table and could send us
down the wrong path for our design.

IEEE Solid-States Circuits Magazine - Summer 2019

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2019