IEEE Solid-States Circuits Magazine - Summer 2019 - 35

Output
Load

+v2f 0
+vf 0

+v2f 0
-vf0

FIGURE 2: A standard push-push oscillator
that generates a second-harmonic signal at
the output.

drain current i d is delayed due to the
propagation along the gate R-L-C network and the finite carrier drift time.
The drain current is further delayed
by the feedforward path through the
parasitic capacitance C gd . To extract
the maximum power from the drain,
the drain voltage v d should phase
match i d . Hence, an extra delay (or
phase shift) of v d is needed in addition to the conventional 180° inversion behavior. If we are off from such
an optimal value, Pout rolls off quickly

id
vd

igd

(Figure 3). This implies that any design that treats and forces the transistor to be a full-inverting device (i.e.,
A = 180°), as we did at a lower frequency, will lead to severe power degradation. Unfortunately, that is exactly
what happens in the popular push-
push oscillator. According to the simulation in Figure 3, the oscillation
power, Pout, is only half the optimal.
The second condition deals with
the optimum harmonic power generation efficiency [32]. This highly
nonlinear problem is simplified into
a harmonic feedback factor, b nf0 .
Normally, harmonic oscillators are
designed for only fundamental-frequency operation, with, at most, an
output-matching network at the desired
harmonic. However, an aspect that
has been neglected is that, once the
harmonic signal is generated from the
transistor drain, it is partially sent back
to the gate through the oscillator structure. Unfortunately, in most (if not all)
previous THz designs, a negative feedback loop is unintentionally formed,
greatly reducing the harmonic output
power. Again, take the push-push oscillator as an example. As mentioned previously, the second-harmonic voltages
on both sides are identical (Figure 2),

vg
Gate

Drain
n+

ich
p-Sub
(a)

Extra Delay
(∆φ1 + ∆φ2)

Source

vd
vg

Output Power Pout (mW)

is allowed to occur only below fmax,
its harmonics may lie well within the
THz region. A push-push secondharmonic oscillator (and its variants)
is a typical topology based on such a
principle. As shown in Figure 2, the
two transistors oscillate in a differential pattern. The fundamental signal
is therefore canceled at the output,
and the second-harmonic signals are
in phase and combined and extracted
to the load.
Although a push-push oscillator was very popular in THz design
[28]-[30], the output power was low, as
explained in the following. In general,
we need to optimize two processes to
maximize the output power. First, at
the fundamental frequency, the transistor should be configured so that
the maximum power is generated to
overcome the passive loss and sustain a large oscillation swing. Second,
the nonlinearity of the device should
be optimized to convert (part of) the
fundamental power into higher harmonics. Regarding these, we find
that two optimization conditions are
required. Because they are derived
from the analysis of a single device,
they are independent of any circuit
topology and hence are very general
and fundamental.
The first condition is called optimum voltage gain at fundamental
oscillation frequency, A opt [31]. Note
that such a gain is a complex value
with both magnitude and phase. If
we model the transistor using a twoport, Y-parameter network and derive
the net radio-frequency (RF) power
Pout coming out of the device, an optimum drain-to-gate voltage ratio (i.e.,
voltage gain) A opt exists, which maximizes the power. (The net power is
the sum of two parts: that generated
from the drain and that dissipated by
the gate.) In particular, we find that,
close to fmax, the phase of the gain
is significantly smaller than 180° (or
more negative than -180°, considering
the device delay).
We can better comprehend such
a phenomenon from a device point
of view, as shown in Figure 3 [32].
When a gate voltage is applied, the

0
igd

∆φ1
∆φ2 i

120

150 180
∠A (°)

210

(c)

id
(b)
FIGURE 3: (a)-(b) The phase delays of various voltage and current components inside a transistor that lead to the optimum complex voltage gain condition. (c) The calculated (dashed line) and
simulated (solid line) net output power at 130 GHz of a 65-nm NMOS transistor (fmax = 200 GHz)
with varying phases of the gain [32].

IEEE SOLID-STATE CIRCUITS MAGAZINE

SU M M E R 2 0 19

IEEE Solid-States Circuits Magazine - Summer 2019

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2019