IEEE Solid-States Circuits Magazine - Summer 2019 - 47

With IMC recently becoming an active
research area, we have seen a number of prototype demonstrations
that enable comparisons against
digital-accelerator approaches. Figure  6(a) plots the area-normalized
throughput versus energy efficiency
of recent IMC and non-IMC prototypes, showing that IMC enables
roughly 10× gains in each metric,
which is expected based on the
aforementioned analysis. Although
this represents significant promise, Figure 6(b) exposes the primary
challenge: plotting the total scale of
computation achieved (the amount
in memory integrated in prototypes).
With the exception of one design [11]
(considered in detail in the "HighSNR Circuit Design" section), IMC
demonstrations have been highly
limited in scale, primarily due to the
fundamental SNR tradeoff described,
especially in the context of analog
computation. The following section
takes a closer look at the challenges,
using recent demonstrations as examples, to then motivate possible
paths forward.

IMC Challenges and Approaches
Multiple IMC approaches have recently
been proposed. To frame this discussion, it is useful to relate these to the
fundamental tradeoffs developed in
t he " B a ndw idt h/ Latency/E nerg y
Versus Signal-to-Noise Ratio Tradeoff" section. For example, although
some designs perform computation in
memory, they may activate only one or

Normalized Throughput (GOP/s/mm2)

Current Standing of IMC

two WLs at a time (e.g., [13] and [14]).
This prevents significant amortization compared to standard memory
accessing, yet it incurs the challenges of integrating computation in constrained bit-cell circuits (e.g., [13]
requires adopting a 10-T bit cell, and
[14] requires multiple memory-operation cycles). In such cases, standard
memory accessing would likely be
preferable, followed by computation
just outside the memory array using
less constrained circuits. Keeping in
mind the fundamental IMC tradeoffs, the following sections survey
the challenges, illustrated using recent
design examples.

10e4

Circuit Challenges
Analog Nonidealities
To fit computation in constrained bitcell circuits, IMC commonly employs
analog operation, leveraging richer T
behavior than that allowed by digital
switch-based abstraction. With regard
to the SNR tradeoff, the increased
sensitivity to variations and nonlinearities now becomes the dominant
source of computation noise. For
instance, Figure 7 shows the nonlinearity and variation (standard deviation shown as error bars) of the BL/
BLb output with respect to one inputvector element value in [7] and to the

Khwa, ISSCC'18, 65 nm
Zhang, VLSI'16, 130 nm

IMC
Not IMC

10e3

Valavi, VLSI'18, 65 nm
Jiang,
VLSI'18,
65 nm

Lee, ISSCC'18, 65 nm
Moons, ISSCC'17, 28 nm
Ando, VLSI'17, 65 nm
Shin, ISSCC'17, 65 nm

10e2

Biswas,
ISSCC'18, 65 nm

Bankman,
ISSCC'18, 28 nm
Chen, ISSCC'16, 65 nm
Gonug,
ISSCC'18, 65 nm
Yuan, VLSI'18, 65 nm
Yin, VLSI'17, 65 nm

10

10e-2

10e-1
1
10
10e2
Energy Efficiency (TOP/s/W)
(a)

10e2

10

Yin, VLSI'17, 65 nm
Yuan, VLSI'18, 65 nm
Ando, VLSI'17, 65 nm
Chen,
ISSCC'16,
65 nm
Gonug,
ISSCC'18, 65 nm

Bankman,
Moons,
ISSCC'18,
ISSCC'17,
28 nm
28 nm

Biswas,
ISSCC'18, 65 nm

1

Jiang,
VLSI'18,
65 nm

Khwa, ISSCC'18, 65 nm

10e-2

10e3

Valavi,
Lee,
ISSCC'18, VLSI'18,
65 nm
65 nm

10e3
On-Chip Memory Size (kB)

for multibit computation. Namely,
although IMC bit cells can perform
1-b logical operations (XNOR and
AND), digital PEs require multibit
operation (full adder). As we will
show, such amortization once again
imposes an SNR tradeoff. Using silicon measurements and postlayout
simulations in a 45-nm technology,
we see that, over the storage, multiply, accumulate, and data-movement
operations performed by PEs, IMC
holds the potential for 10× greater
energy efficiency.

10e-1
1
10
10e2
Energy Efficiency (TOP/s/W)

Zhang,
VLSI'16,
130 nm
10e3

(b)
FIGURE 6: A comparison of IMC and non-IMC prototypes: the (a) throughput versus energy
efficiency and (b) total memory versus area efficiency.

IEEE SOLID-STATE CIRCUITS MAGAZINE

SU M M E R 2 0 19

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IEEE Solid-States Circuits Magazine - Summer 2019

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