IEEE Solid-States Circuits Magazine - Summer 2019 - 48

overall accumulation result in [15].
Additionally, using T currents as the
output signal of each bit cell also
raises sensitivities to temperature,
which can strongly impact carrier
transport in semiconductors.
One way to mitigate the effects
of T nonlinearity arising from BL/
BLb biasing is to employ low-swing
signaling. However, the SNR tradeoff is then adversely affected by the

Ideal
IdealTransfer
TransferCurve
Curve
0.06
0.06

BL (V)
(V)
VVRBL

∆VBL (V)
(V)
∆V
BL

0.32
0.32VV

0.3
0.3

0.28
0.28VV

0.2
0.2

0.02
0.02
Nominal
NominalTransfer
TransferCurve
Curve
55 10
10 15
15 20
20 25
25 30
30 35
35
WLDAC
WLDACCode
Code
(a)
(a)

pulsewidths are applied in parallel
for binary weighting, thereby yielding an analog read operation of a multibit word (configurable mixed-signal
computation is then performed in the
array periphery).
An important direction for IMC
is incorporating alternate memory
technologies-for instance, nonvolatile technologies-that can enable
the possibility of multilevel storage, low-power duty-cycle operation,
and increased density. The emerging memory technologies can include
resistive RAM (RRAM), magnetic RAM
(MRAM), and phase-change memory
(PCM). Such technologies suffer from
many of the same analog nonidealities as SRAM-based IMC. For instance,
Figure  9(a) shows the variation of
MAC outputs from a NOR-flash implementation [8]. On top of this, such
technologies are likely to exacerbate
the challenges with analog readout.
For instance, multilevel storage further increases dynamic-range requirements, impacting the SNR tradeoff,
and the relatively low resistance and
low-resistance contrast of emerging memory technologies (RRAM and
MRAM) increase the power and area of
the readout circuitry, which already
dominates in demonstrated systems
[9], as shown in Figure 9(b).

0.6
0.6 Measurement
Measurement
0.5
0.5
0.4
0.4

0.04
0.04

00

increased impact of variations (and
shot-noise sources) relative to the
signal. In fact, higher computation
SNR may be observed in practice by
increasing swing [16]. Nonetheless,
Figure 8 illustrates the approach
in [16], also showing that the MAC
operation possible in IMC columns
can be used beyond MVMs. In this
case, multibit data are stored in a column-major format, and different WL

0.1
0.1
0.0
0.0

-256 -128
-128 00 128
128 256
256
XAC
XACValue
Value
(b)
(b)

FIGURE 7: An illustration of analog-computation nonidealities: (a) the BL/BLb-discharge nonideality in [7] and (b) the read-BL nonideality in [15]. XAC: XNOR-and-accumulate value.

T3 = 8T0

VPRE

VBL

Prech
6T-SRAM Bit Cell VBLB

VWL0

CWL

d0

VWL1

CWL

d1
CBL

VWL3
VWL2
VWL1
VWL0
VBL

CBL

T2 = 4T0 T1 = 2T0

8∆VIsb

4∆VIsb

d2

d3

T0

∆VBL (D)
2∆VIsb ∆V
Isb

d1

Power Delivery

d0

IMC leverages the parallel structure of memory. However, such parallel operation also elevates peak

FIGURE 8: An analog readout of multibit data stored in bit-major format [16].

Chip 4

0.6
0.3
0

 = 1/160,000x
∑(Vmeas - Vsim)/Vsim= 0.07

0
0.3
0.6
Simulated Value (V)

Input
Input
Register Register

Measured Value (V)

0.9

a0

a1

DAC

DAC

0.9

(a)

SL[0]

BL[0]

w00
SL[1]
w10
ADC

b0
Output
Register

BL[1]

WL[0]
= VDD

w01

WL[1]
= VDD

w11
ADC

b1
RG Output
Register

RG

Challenge 1
28% 48%

86% 11%

ADC

Energy

Area

DAC
RRAM

24%

3-b ADC and DAC are adopted in this evaluation.
ADC and DAC overheads.

Challenge 2
SL[1] = 0

WL[1] = VDD
w11

Leakage Current

i=

VBL[1] - 0
R
VBL[1]

(b)

FIGURE 9: The challenges with nonvolatile memory technologies: the (a) variation of MAC outputs [8] and (b) energy/area consumption of
readout circuity [9]. ADC: analog-to-digital converter.

48

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IEEE Solid-States Circuits Magazine - Summer 2019

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