IEEE Solid-States Circuits Magazine - Summer 2019 - 49

Bit-Cell Stability
A consequence of accessing computational results rather than raw data
is that activated bit cells are exposed
to different data on BL/BLb than
those stored. This raises the possibility of disrupting their stored data.
Two approaches have been pursued
to guard against this. First, buffered
cells have been employed, whereby
the critical data-storage nodes are
isolated from the computed BL/BLb
value [15]. This has the drawback of
degrading density. Second, suitable
bit-cell biasing has been employed.
This has included low-swing signaling on BL/BLb such that bit-cell
biasing remains close to standard
SRAM read-condition biasing [16].
However, this adversely affects the
SNR tradeoff. Alternatively, WL-biasing has been employed, wherein the
WL voltage is kept low [7]. In addi-

istically different than MVM in that
they apply to element-wise (low-/single-dimensionality) operands. This
reduces the emphasis on data movement that motivates IMC and instead
enables the use of conventional digital acceleration. However, it is critical that IMC now integrates robustly
and efficiently in larger heterogeneous architectures.
This raises two critical considerations. First, robust integration in
larger architectures requires a welldefined functional specification of
the IMC block. This is challenged by
analog circuit nonidealities, which
significantly affect computation SNR
and are typically difficult to characterize (e.g., due to process, temperature,
and voltage dependence) or statistical
in nature (e.g., due to T variations).
Second, heterogenous architectures
are often limited by data movement

tion to limiting the bit-cell current
to guard against BL/BLb saturation
in dynamic computation, this can
ensure adequate isolation of the
bit-cell storage nodes from the computed BL/BLb value.

Architectural Challenges
IMC primarily addresses MVM or
other vector operations, which represent only a subset of computations
required in practical applications.
As an example, Figure 11 shows the
profiling results for the many computations required in different neuralnetwork (training) applications [17].
Although we see that MVM (shown as
general matrix multiply) dominates,
it is necessary for complete architectures to address the many other computations and to do so programmably
and configurably. Importantly, the
other computations are character-

Measurement at VDD = 0.6 V
BL Voltage (V)

800 µ
Power (W)

power-delivery requirements in
at least two ways. First, activation of
many/all WLs is fundamental to the
amortization performed and thus
requires corresponding power delivery to the WL drivers. This must be
addressed through power-grid density,
especially because noise on the WL
levels can translate directly to computation noise. Second, operation of
many/all bit cells is fundamental to the
amortization performed. We can make
a distinction between static and
dynamic computation approaches.
Figure 10(a) shows an example of static
computation, employing a static buffer at the bit-cell output [15]. In this
case, activating many/all bit cells leads
to currents of up to 1 mA in each column, challenging the feasibility of
low-noise power delivery. Figure 10(b)
shows an example of dynamic computation, where the activated bit cells
simply discharge the BL/BLb capacitance such that the total charge delivered never exceeds that of a standard
full-swing read [7]. This requires designing against saturation of BL/BLb
discharge, as is done in [7] by restricting WLDAC output range and minimizing BL/BLb leakage, which can result
in computation noise.

600 µ
400 µ
200 µ
0

1 mA /Column
-256 -128
0
128
XAC Value
(a)

1.2
1
0.8
0.6
0.4
0.2
0

BL
BLb

256

4
6
8
Time (ns)
(b)

FIGURE 10: An illustration of power-delivery considerations in IMC: the (a) static current
drive [15] and (b) dynamic current drive [7].

BN50
Speech
Charr
(RNN)
anguage
Language
LSTM
(DNN) Nat Lang
VGG
Vision
(CNN) AlexNet
0
gemm
calcError
axpy

lowering
tanh
saturate

General Matrix Multiply
(~256 × 2,300 = 590-k Elements)

softmax
tanhGrad
relu

50
(%)

rnorm1
sigmoid
reluGrad

100

rnorm2
sigmoidGrad
matrix assign

Single-/Few-Word Operands
(Traditional, Near-Memory Acceleration)

FIGURE 11: The range of computations required in neural-network applications [17]. BN:
batch normalization; Char: character level; LSTM: long short-term memory; Nat Lang: natural
language.

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IEEE Solid-States Circuits Magazine - Summer 2019

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