IEEE Solid-States Circuits Magazine - Summer 2019 - 51

readout challenges (e.g., to manage
possible interference between readout columns), making the readoutcircuit area significant and, again,
scaling with array size. On the other
hand, one-T, one-resistor (R) structures are typically denser than SRAM
but now limited by MOSFET scaling.
Further, the asymmetry in device
characteristics between the T and
R (memory device) often imposes
additional area overheads to resolve
(e.g., the use of two complementary
bit cells).
An additional motivation for emerging resistive memory technologies is
nonvolatility, which has the potential to lower power, especially in
duty-cycled scenarios. This holds significant promise but will need to be
evaluated in application use cases.
Additionally, nonvolatility often limits the number of write cycles, posing
challenges for hardware-virtualization approaches.

Algorithmic Codesign
Machine-learning inference has emerged
as one of the biggest drivers for IMC,
both because the computations have
driven platforms to their energy
and throughput limits and because
the computations are dominated by
MVM, which limits the gains possible
from digital accelerators. Interestingly, machine-learning inference
presents distinct opportunities for

Backward

Prediction y

L = y - y(x, θ, G)2

90
80

Loss Function L

Model
Parameters
θ (x, G, L)

70
60
50
40
30

L = y - y(x, θ)2

20
Prediction
y (x, θ(L), Zi )

Noisy
Forward

Testing

100

Noisy
Forward

This has the drawback of incurring
instance-by-instance training costs,
and recent IMC demonstrations have
explored incorporating the associated
hardware support to minimize such
costs [19]. In hardware-generalized
training, a statistical model of the distribution of variation-affected hardware is used in the training process
to learn parameters one time [20].
This avoids the need for instanceby-instance training. For the example
shown in Figure 13 of MRAM-based
IMC implementing a neural network
for vision classification (CIFAR-10), we
see that this can overcome significant
variation in the hardware (accuracy is
maintained at several multiples of the
actual MRAM-conductance variation).
Such algorithmic approaches show
considerable promise, presenting a
rich area for research. Specifically, a
critical challenge that will need to be
addressed is that operation relying
on algorithmic codesign will inherently disrupt hierarchical abstraction
based on the functional specification employed in architectural design
today. Thus, new, possibly statistical
approaches to composable architectural design and application mapping
will likely be required.

MRAM-Based BNN Simulation
(Applied to CIFAR-10)

Accuracy

addressing the SNR tradeoff in IMC
through algorithmic approaches.
Machine-learning inference involves
specifying a parametric model of
how data statistically relate to inferences (decisions) of interest and then
training the model parameters using
available data that are representative
of the statistics. In this way, statistical parameter optimization for a
given model affords flexibility in the
choice of actual model, which can
be selected for computational efficiency. For example, this aspect has
been exploited toward aggressive
quantization [2], which has already
been shown to yield benefits for IMC.
But it can also be exploited to overcome computational noise arising
from analog circuit nonidealities limiting IMC.
Because the nonidealities can be
statistical (e.g., variations) or deterministic (e.g., nonlinearity), a distinction
can be made between hardware-specific training of model parameters
and hardware-generalized training of
model parameters. In hardware-specific training, the specific variationaffected instance of hardware is used
in the training process to tune parameters to the specific hardware [7], [19].

Training

Instead of accessing raw bits row by row, IMC
accesses a computation result over many/all bits,
thereby amortizing the accessing costs.

3
4
5
6
7
8
9
Normalized MRAM Cell Standard Deviation

FIGURE 13: An illustration of an algorithm approach to overcome analog nonidealities [20]. BNN: binarized-neural-network.

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IEEE Solid-States Circuits Magazine - Summer 2019

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