IEEE Solid-States Circuits Magazine - Summer 2019 - 63

mechanism used in thyristor-based
PUFs (i.e., PMOS and NMOS transistors whose drain drives the gate of the
other), as seen in Figure 8(b). In this
PUF, the output nodes Gp and Gpl
in Figure  8(b) are first precharged to
the supply voltage and then let free to
discharge toward the ground [47]. The
output bit is determined by which side
is faster and, thus, by mismatch.
The class of static monostable PUFs
introduced in [105] is based on PUF bit
cells that generate a static output and
have only one stable state. The static
behavior assures that the output is
independent of coupling noise and insensitive to routing (as opposed to, for
example, delay-based PUFs). Monostability ensures that the correct output
bit is delivered, even when occasionally intense transient noise flips the
bit cell (as opposed to memory-based
PUFs). This is achieved by connecting
back-to-back current mirrors, as in
Figure  8(c), where the output is high
(low) if the PMOS (NMOS) current mirror is stronger than the other due to
mismatch. The output is essentially
full swing because of the inherently
high small-signal output resistance of
current mirrors, which assures a large
output voltage change under a small
PMOS/NMOS current mismatch [105].
This PUF has been shown to be
suitable for the standard cell layout style and also to be placementindependent because of negligible

1E+05
1E+04
1E+03

Area per Bit

Energy per Bit

1.4×/
y
1.3×/
y

1E+04

ear

ear

1.18×
/

year

1E+03

1.44×

/year

1.04×/year

1E+02

1.35

×/ye
a

r

1E+02
1E+01
1E+00
1E-01

~Constant

ye
×/

ear

1.28×/y

23
2.

Energy (pJ/b)

1E+06

rupture [91], [92] by applying a stress
voltage in transistor pairs, the response bit being determined by which
transistor breaks first. In this PUF, a
resistive path is created between the
gate and drain of the transistor experiencing breakdown, while the other
does not have such a direct gate-drain
path. Although highly stable and area
efficient, these circuits are actually not
PUFs, strictly speaking. Indeed, their
physical inspection (e.g., delayering
and imaging) can potentially reveal the
secret bits. In addition, PUF responses
are available even when the device
is powered off, as the information is
stored in a nonvolatile manner, thus
violating the previously described fundamental PUF properties.
A thorough review of PUF state
of the art and related technological
trends is available in the PUFdb in [69].
Based on the PUFdb data, the trend of
the area per bit in Figure  9(a) shows
that PUFs are generally becoming
more area efficient over time, with the
metastability and static monostable
classes exhibiting the largest improvement of 1.4×/year, as expectable from
their digital nature. The area of analog PUFs is instead stagnant due to the
expectedly slow shrinkage of analog
circuits across CMOS generations. As
shown in Figure  9(b), the digital nature of metastability-based and static
monostable weak PUFs has enabled
a rapid improvement in the energy

×/y
3.5

1E-02

1E+00
1999 2002 2005 2008 2011 2014 2017 2020
Year
(a)

1E-03
1999 2002 2005 2008 2011 2014 2017 2020
Year
(b)

Analog

Delay

Memory

Metastability

ar

1E+01

ear

Normalized Area/Bit (F2)

1E+07

layout-dependent variations. This is
achieved by crafting the bit-cell layout
to homogenize the layout environment
around the mismatch-critical transistors (i.e., current mirrors) across all
bit cells, keeping them at the center
of the bit cell, and consistently adding
decaps next to the bit cells. The resulting bit cells can be freely placed and
routed to design PUFs in a matter of
hours rather than several weeks using
a fully automated digital design flow
[86]. This is different from other
PUFs that require significant design effort in view of the analog-style bit-cell
layout and design (e.g., a ring oscillator) or array organization (e.g., metastability based). In [86], hysteresis and
temperature compensation have been
added to improve PUF stability. For
another example of a PUF in the same
class, two-transistor voltage generation and mismatch amplification via
two-transistor gain stages have been
demonstrated in [96].
A recently proposed highly stable
and ECC-less class is based on the induction of the random presence or absence of a resistive path in the bit cell.
This is achieved at manufacturing time
by the via PUF [106] purposely violating the via spacing design rules to randomly create shorts or open circuits in
pairs of neighboring vias, depending
on random manufacturing imperfections. A similar outcome is achieved at
testing time through intentional oxide

Monostable

FIGURE 9: State-of-the-art PUF trends: (a) area (normalized to F 2, where F  = minimum feature size of the process) and (b) energy
consumption [69].

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IEEE Solid-States Circuits Magazine - Summer 2019

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