IEEE Solid-States Circuits Magazine - Summer 2020 - 13

From another view point, a DT integrator adds its present input to the
sum of its past inputs. That is,
	

y [k] = x [0] + x [1] + g + x [k] (17)

	

= y [k - 1] + x [k] .(18)

x

1

1 - z -1

x

1 - z -1

H (z )

(a)
+

x [k ]

y [k ]
+

It follows that

α<1
0

z -1

	

α=1

1
1 -α

2

Y (z) = z Y (z) + X (z) (19)

(c)

(b)

and hence
	

Y (z)
1
. (20)
=
X (z)
1 - z -1

T he circuit cha racter ized by
(1 - z -1) -1 is called a nondelaying integrator. If the delay stage is placed
in the forward path (Figure 14), we
obtain Y/X = z -1 / (1 - z -1) and call
the structure a delaying integrator.
Except for the one-cycle delay, this
topology has the same properties as
the nondelaying counterpart.
The ver y high gain prov ided
by the integrator near f = 0 results from the fact that z -1 " 1 and
proves useful in many applications.
For example, suppose a circuit experiences additive noise at its output [Figure 15(a)]. This can occur in
the digital domain if the output of
a register is truncated (quantized).
We precede this stage by a delaying
integrator and embed the cascade
in a negative-feedback loop, as in
Fig --u re 15(b). The noise now experiences a transfer function given by
	
	

Y (z)
=
N (z)

x [k ]

+

z

input must vary even more slowly than
in a 1 - z -1 system to cancel its replica. That is, the high-pass corner frequency is reduced. Moreover, writing
1 - z -2 = (1 - z -1) (1 + z -1), we recognize that this system comprises a cascade of an HPF and an LPF (Figure 17).
As another example, consider
a 1 + z system. Since we have
1 + z = z (1 + z -1), the system advances (shifts to the right) the input signal
by one clock cycle and then subjects
it to an LPF. Similarly, 1 - z is equal
to z (1 - z -1) and hence equivalent to
a one-cycle advancement followed by
an HPF.

y [k ]

-1

+
FIGURE 14: A delaying integrator.

insights. Let us return to LPFs and
consider the two transfer functions
H 1 (z) = 1 + z -1 and H 2 (z) = 1 + z -2.
Recall from Figure 4 that a slowly
varying signal and its delayed replica tend to add constructively. For
H 2 (z), however, the signal is delayed by two clock cycles and must
therefore vary even more slowly for
constructive addition. This means
that H 2 (z) exhibits a narrower bandwidth than H 1 (z) does [Figure 16(a)].
The slower step response in Figure 16(b) confirms this point as well.
Next, we study a 1 - z -2 system.
Owing to the two-cycle delay, the

Stability
For CT systems, the transfer function's poles must remain in the left
half s plane to ensure stability. Poles
on the j~ axis lead to constant-amplitude sinusoidal oscillation, and

n

= 1 - z -1 .(22)
1
x [k ]

+
+

y [k ]

(a)
Integrator
x [k ]

+

+
-

z -1

n
1

+
+

y [k ]

+

(b)

Other Insights
Analyzing z-transforms in terms of
the unit delay, z -1, offers further

	

FIGURE 13: (a) The cascade of a differentiator and an integrator, (b) an integrator realization, and (c) the frequency response of the integrator.

1
(21)
-1
1 + z -1
1-z

The differentiation action supp-
resses the low-frequency noise components. This occurs because the
integrator in Figure 15(b) provides a
high loop gain near f = 0, strongly
opposing the injection by n. We say
the noise spectrum is "shaped." Note
also that, except for a one-cycle delay, the input-output transfer function is equal to unity.

f

fCK

-1

FIGURE 15: (a) A stage experiencing additive noise at its output and (b) the shaping of the
noise spectrum through the use of negative feedback.

	 IEEE SOLID-STATE CIRCUITS MAGAZINE	

SU M M E R 2 0 2 0	

13
IEEE Solid-States Circuits Magazine - Summer 2020

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