IEEE Solid-States Circuits Magazine - Summer 2020 - 19

First, typical VCO nonlinearity can
be tackled using proper feedforward
and feedback architectures. Second,
the problem of poor phase noise and
jitter performance can be overcome
by applying suitable sizing and circuit techniques, such as chopping.
Third, the assumed poor robustness
due to temperature and power supply
variations (power-supply rejection),
drift, and aging can be surmounted
with techniques as simple as using
a pseudodifferential configuration
or as complex as setting up a complete closed-loop circuit. Thanks to
advancements like these that overcome the negative properties of circuit blocks such as VCOs, the resulting
systems can be very compact while
achieving excellent performance.
Additionally, similar to conventional
continuous-time delta-sigma modulators, VCO-based ADCs exhibit an
intrinsic antialiasing filtering property. Combined with their very high
sensitivity [3], [4], this allows for the
elimination of other traditional analog blocks such as preamplifiers and
antialiasing filters.
We conclude this article by presenting the current state of the art in
VCO-based ADCs, as published in the
literature. Together, both overview
articles demonstrate how time-encoding circuits can overcome the struggles
of designing high-performance analog
circuits in advanced digital CMOS technologies, fully taking advantage of-
rather than suffering from-process
scaling, hence bridging the analog gap
to advanced nanometer CMOS.

Architectures for Improved Linearity
A notorious issue in ring-oscillator
VCOs is their highly nonlinear tuning
response. For virtually every type of
VCO tuning, a tuning curve similar to
that shown in Figure 1 (whether bottom or top driven) is obtained, which
is catastrophically nonlinear. A standard technique to improve this is
the use of a pseudodifferential setup
(see the discussion in part one [3]).
However, even then, the large-signal
linearity is still far from acceptable
for most applications. An obvious

The problem of poor phase noise and jitter
performance can be overcome by applying suitable
sizing and circuit techniques, such as chopping.
solution for this is to greatly restrict
the input range of the VCO, i.e., use
the VCO in the small-signal regime.
This strategy can often be followed
directly in sensor applications, where
the input signals are typically small;
because the bandwidth is typically
very low as well, the loss in dynamic
range due to the limited input range
can be easily compensated for by a
large oversampling ratio. However,
for larger bandwidths, this straightforward approach is less obvious,
and more sophisticated architectural

solutions come into play. In the following sections, we discuss the use
of the most important approaches:
1) overall feedback architectures, 2)
input feedforward architectures, and
3) calibration.

Closed-Loop, VCO-Based
ADC Architectures
The basic architecture of a large
family of closed-loop, VCO-based
ADC structures [5]-[9] is shown in
Figure 2. The structure consists of
two (nominally matched) VCOs in a
differential feedback loop. The VCOs
are driven by the difference between
the (differential) input signal and
the converted digital output fed
back. The outputs of the two VCOs
drive a phase detector. The observed
phase difference steers the loop
toward phase equilibrium. Many
possibilities exist for the implementation of the phase detector, ranging
from structures such as those used
in phase-locked loops (PLLs) [6], [9]
to counter-based structures [7], [10],
as depicted in Figure 2. The phase
detector shown in the figure uses
only one VCO output phase, but it
is also possible to use multiple VCO
output phases for improved performance [3]. The underlying mechanism of this architecture can be
readily understood by reasoning on
the established phase-domain model
of a VCO as an integrator (see part

fVCO

(a)

Vtune

fVCO

(b)

Vtune

FIGURE 1: The typical shape of the tuning
curve of a ring-oscillator VCO, showing
large nonlinearity. The curves corresponding to (a) bottom- and (b) top-driven VCOs,
respectively.

DACp
−
Vin,+

+
+

Vin,-

−

KVCO, fo
+

Multibit Phase Detector
fs

VCO1
Up
Down

Counter

Sampling
Register

Dout(z)

VCO2
DACn

FIGURE 2: The simplified diagram of a large family of closed-loop, VCO-based ADC
architectures.

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IEEE Solid-States Circuits Magazine - Summer 2020

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