IEEE Solid-States Circuits Magazine - Summer 2020 - 22

and 80-dB signal-to-noise and distortion ratio) in [34]. On the other side
of the spectrum, for sensing applications with low bandwidth but high
resolution, the authors of [35] have
presented a 1−1 sturdy-MASH architecture with the second loop and its
integrator built entirely in digital circuitry, achieving second-order noise
shaping and 16.1 bits of resolution.

Combining multiple VCO ADCs on
the same chip and then averaging the
conversion result is also a potential
option. This concept is known as a
stochastic VCO ADC [36]. In principle,
this technique does not increase
power, because the power increase
due to multiple VCOs in parallel is
compensated for by the reduction
in thermal noise (after averaging),

DAC
−
Vin,+

+

+

VCO1

fs

Phase
Readout

NCF2
+

Error
Extraction

VCO1

Time-Domain Chopping

NCF2

fs

Phase
Readout

Dout (z)

1-z -1

FIGURE 7: A 1−1 MASH VCO-based ADC with second-order noise shaping [34]. NCF: noisecancellation filter.

VCO1

Cfixed

+

Multibit
Phase
- Detector

Dout

VCO2

Cdig

Csense

(a)

Differential
IDAC
VCO1

+

Multibit
Phase
- Detector

VCO2

Sensor
Resistors

Digital
Filter

Dout

(b)

FIGURE 8: The introduction of time-domain chopping in a closed-loop, VCO-based ADC
structure with a sensor in the loop: (a) the combination of VCOs and a phase detector is
chopped [11], and (b) only the VCOs are chopped [13]. IDAC: current-mode DAC.

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SU M M E R 2 0 2 0	

IEEE SOLID-STATE CIRCUITS MAGAZINE	

similar to impedance scaling for a
single ADC channel. In addition to
circuit noise averaging, quantization noise is also averaged. This is
because, in a properly designed
stochastic VCO ADC, the quantization noise contributions of each ADC
channel are uncorrelated. In this
way, in principle, this stochastic concept is very simple, power efficient,
and digital friendly: all the designer
needs to do is design a simple lowpower VCO ADC channel and then
put as many channels in parallel as
needed to achieve the desired accuracy [36], [37]. In practice, however,
most recently published designs are
still far from the state of the art in
terms of performance.

Circuit noise is an important limitation in any analog circuit, including
VCO-based ADCs. Although many
designers think about VCO noise in
terms of oscillation phase noise, we
advocate considering this in terms
of input-referred circuit noise (see
also part one [3]), similar to amplifier noise. The white noise translates
to a very conventional noise-versuspower tradeoff. The 1/f noise in
traditional amplifiers is addressed
in two ways: 1) by sizing the noisedominant devices using a large area
and/or 2) by deploying chopping. In
a similar way, suitable sizing strategies have been deployed to tackle
1/f noise in VCO-based ADCs by
properly sizing the inverting-stage
transistors (e.g., [35] and [38]) or by
increasing the number of VCO taps
(such as in [27], [39], and [40]) as far
as the targeted bandwidth allows.
To achieve higher resolutions,
time-based chopping techniques
have been introduced and demonstrated successfully, in particular for sensor readouts where the
bandwidth is relatively low, making it difficult to push the 1/f noise
sufficiently low by sizing only [11].
Two examples of this are shown
in Fig u r e 8: in Figure 8(a), both
VCOs and the phase detector are
embedded inside the choppers [11],
IEEE Solid-States Circuits Magazine - Summer 2020

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