IEEE Solid-States Circuits Magazine - Summer 2020 - 43

Vin
Sawtooth Vs
-
Generator
+
Pulsewidth
Modulator

PWM
Vsw

Power Stage
S1
Vout
L
S2

ton
Vsw

PWM

Iout

On Time ton

Vin

C
G (s )

Compensator
Vc
Zo

gm-
+ Vref
Error Amp

Vc

T = 1/fsw

Vfb Rfb1

Vout = (ton/T )V in

Rfb2

Vs

H (s )

t

(a)

t

(b)

(c)

FIGURE 1: (a) A dc-dc converter with waveforms for (b) typical node voltages and (c) pulsewidth modulation (PWM) generation.

have two tasks: 1) they form a lowpass filter, which generates the dc-dc
converter's output voltage as the average of the switching node voltage
Vsw, and 2) they buffer the energy to
supply the load while S1 is off. In the
ideal case, the static on-off states of
the switches are not associated with
any losses. In reality, this kind of
converter can still reach power efficiencies much higher than 90%. The
output voltage can be controlled by
varying the pulsewidth at the switching node, which points to pulsewidth
modulation (PWM) as a key concept
in dc-dc converters. High-switching
frequencies fsw result in smaller passives. Although state-of-the-art converters operate at a few megahertz,
advanced designs reach 20-30 MHz
and higher [1]. Challenges include
high-speed circuits such as gate
drivers and level-shifters as well increased switching losses and parasitic coupling.
The control loop in Figure 1(a)
contains an error amplifier ("Error
Amp") that compares the set point
given by Vref with a down-scaled value of Vout. Hence, its output voltage
Vc is a measure of the output deviation (the error). The error amplifier
is also referred to as the compensator because it shows the certain frequency behavior needed to keep the
loop stable (set by Z o). If S1 turns on
for PWM = 1, a sawtooth generator
gets activated [see Figure 1(c)]. As
soon as the ramp voltage Vs exceeds

Although state-of-the-art converters operate
at a few megahertz, advanced designs reach
20-30 MHz and higher.
the error voltage Vc, the PWM resets
to zero. A load step at the output
will pull down Vout slightly. Due to
the inverting behavior of the com-

pensator, Vc increases and causes
Vs to cross at a later point in time.
As the on time of the PWM pulse
increases, S1 brings more energy

Low-Side Switch
Drain
VD < 0

Sensitive Circuits
Substrate =
Ground
Isub

!

Gate
p+

n+

n+

p+
n

p -Substrate
(a)
Substrate = Ground

Drain
VD < 0

Isub

Gate
p+

n+

p+

n+

p+
n

n
Isub ~ 0

p -Substrate

(b)

Guard Ring

FIGURE 2: (a) A power switch cross section with parasitic junctions that forms a parasitic
n-p-n transistor. (b) A surrounding guard ring prevents parasitic currents from propagating
toward sensitive circuit blocks.

	 IEEE SOLID-STATE CIRCUITS MAGAZINE	

SU M M E R 2 0 2 0	

43



IEEE Solid-States Circuits Magazine - Summer 2020

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2020

Contents
IEEE Solid-States Circuits Magazine - Summer 2020 - Cover1
IEEE Solid-States Circuits Magazine - Summer 2020 - Cover2
IEEE Solid-States Circuits Magazine - Summer 2020 - Contents
IEEE Solid-States Circuits Magazine - Summer 2020 - 2
IEEE Solid-States Circuits Magazine - Summer 2020 - 3
IEEE Solid-States Circuits Magazine - Summer 2020 - 4
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