IEEE Solid-States Circuits Magazine - Summer 2020 - 44

Active integrators allow for shifting the starting
point and endpoints of the ramp such that they
fit to the common-mode range at the error
amplifier's output and the comparator's input.
into the -system and counteracts the
load step. Hence, a stable control is
achieved by varying the duty cycle
at the power stage. The ramp generator may be as simple as a current source that charges a capacitor.
However, active integrators allow for
shifting the starting point and endpoints of the ramp such that they
fit to the common-mode range at
the error amplifier's output and the
comparator's input.
Any transistor can be utilized as
a power switch (see S1 and S2 in
Figure 1). Low-voltage transistors are
well suited for forming a power de-

vice with fast switching behavior and
a small layout area. Due to their lower
on-resistance, most power switches
are n-type devices. For higher voltages (25 V ), double-diffused MOS
transistors and drain-extended
devices are available in technologies
with high-voltage capabilities. To
achieve a low on-resistance, the drive
voltage VGS = Vdrv should be as large
as possible, typically up to 5 V while
the W/L ratio of the power transistor
is scaled up accordingly. Because capacitive gate charging is associated
with losses, proper switch-transistor sizing requires a tradeoff be-

Level Shifter

Gate Driver

Vdrv

Control
Logic

α

Vsw
α

α

CGD

Voutn

Voutp
IN

Power Switch

Vdrv
α

VDD

tween on-resistance (static losses)
and gate capacitance (dynamic losses).
As the switching node sees an inductive load, it may be pulled below
ground potential during the dead
time while S1 and S2 are off. This
causes the parasitic body diode to become forward biased, as displayed in
Figure 2(a). Any p-n-junction is associated with a parasitic bipolar transistor
structure [2]. In this case, a parasitic
n-p-n device is formed with the body
diode as the base-emitter junction.
Any nearby n-well, perhaps in sensitive analog circuit blocks, will act as a
collector. To prevent any malfunction
and even latch up, every NMOS transistor with its drain connected to a
pin needs to be surrounded by guardring structures that act as the nearby
collector, as shown in Figure 2(b) [2].
The actual power stage consists
of a gate driver and a level shifter
in addition to the power switch, as

Vgate

IN

Cgate

CGS CDS

(a)
Vsw
Strong

Weak

Vdrv

Strong
MP

Weak

Strong

Weak

Weak

Strong

Weak

Vgate

MN
Strong

Weak

(c)

Strong

(b)
FIGURE 3: (a) A low-side power stage with a level shifter and gate driver, (b) a split-path gate driver that eliminates cross currents in the final
driver stage, and (c) a stacking of low-voltage transistors.

44	

SU M M E R 2 0 2 0	

IEEE SOLID-STATE CIRCUITS MAGAZINE	



IEEE Solid-States Circuits Magazine - Summer 2020

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2020

Contents
IEEE Solid-States Circuits Magazine - Summer 2020 - Cover1
IEEE Solid-States Circuits Magazine - Summer 2020 - Cover2
IEEE Solid-States Circuits Magazine - Summer 2020 - Contents
IEEE Solid-States Circuits Magazine - Summer 2020 - 2
IEEE Solid-States Circuits Magazine - Summer 2020 - 3
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