IEEE Solid-States Circuits Magazine - Summer 2020 - 46
For larger power devices, a cascaded driver
approach will result in steeper edges and
lower switching losses in the power stage.
soon as the high-side switch turns
on, D blocks, and C boot delivers the
gate charge for the high-side switch
in addition to leakage and dc currents in the attached circuits. Assuming C boot needs to deliver a charge
of 10 nC, we find that C boot 2 100 nF
if its voltage drop is required to be
below 0.1 V. Hence, C boot is typically
placed off-chip.
Figure 5 shows two high-voltage versions of a cross-coupled level shifter [7] to be used at the high
Soft Start
side to avoid the disadvantages of
the resistive-level shifter. Although
the simple cross-coupled circuit
of Figure 3(a) is restricted to the
maximum source-gate voltage of
the cross-coupled PMOS transistors
(15 V ), high-voltage cascode devices M5 and M6 allow for much higher
values of Vin. The source-gate voltages of M5 and M6 in Figure 5(a)
prevent a zero level (which is equal
to Vsw) at the gate-driver input and
may cause cross currents. This is
addressed by the extended version
in Figure 5(b).
Coming back to the control loop,
a folded cascode design or symmetrical operational amplifier is
suitable for the error amplifier [see
Figure 6(a)], as too much loop gain
may impact stability. At start-up, the
output capacitor C (see Figure 1)
may be fully discharged and cause
large in-rush currents, which result
in component stress, disturbances,
electromagnetic interference issues,
and so on. This can be prevented by
adding a soft-start circuit that bypasses the differential input stage, as
shown in Figure 6(a). C s = 5 pF and
I s = 10 nA result in a typical startup slope within 1-10 V/ms [see Figure 6(b)]. Because I s is very low, it
Error Amp
VDD
IS
VDD
VDD
VDD
Vout
Ibias
Vref
MS
Vc
Vfb
1-10 V/ms
10/1
1/10
10/1
1/10
100 : 1
EN
CS
Ibias = 1 µA Is = 10 nA
t
(a)
(b)
(c)
FIGURE 6: (a) An error amplifier with soft start, (b) a dc-dc converter output at start-up, and (c) the generation of the start-up current.
Zero fz
Rfb2
V
gm (1 + sR1C1)
H (s) = c = -
Vout
Rfb1 + Rfb2 sC1 (1 + sR1C2)
Compensator
Vc
gm
C2
R1
C1
Vfb Rfb1
Vref
Rfb2
Integrator (Pole at f = 0)
|H (s)|/dB
Vout
H (s)
(a)
Pole fp
Vc
R1
k Ic
H (s )
fz
fp
Frequency (log)
C2
Vfb
Vref
Ic
Ry
C11
Buffer
(Voltage Follower)
(b)
FIGURE 7: (a) A frequency compensator, (b) the transfer function H(s) and Bode plot, and (c) the capacitor multiplier.
46
SU M M E R 2 0 2 0
IEEE SOLID-STATE CIRCUITS MAGAZINE
Rx = k Ry
(c)
= k C11
= C1
IEEE Solid-States Circuits Magazine - Summer 2020
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2020
Contents
IEEE Solid-States Circuits Magazine - Summer 2020 - Cover1
IEEE Solid-States Circuits Magazine - Summer 2020 - Cover2
IEEE Solid-States Circuits Magazine - Summer 2020 - Contents
IEEE Solid-States Circuits Magazine - Summer 2020 - 2
IEEE Solid-States Circuits Magazine - Summer 2020 - 3
IEEE Solid-States Circuits Magazine - Summer 2020 - 4
IEEE Solid-States Circuits Magazine - Summer 2020 - 5
IEEE Solid-States Circuits Magazine - Summer 2020 - 6
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IEEE Solid-States Circuits Magazine - Summer 2020 - Cover3
IEEE Solid-States Circuits Magazine - Summer 2020 - Cover4
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