IEEE Solid-States Circuits Magazine - Summer 2021 - 49

of his talk, Wicht gave system- and
circuit-level overviews of the current
and future challenges. Beginning with
the basic question of how to convert
12 V to 2 V, Wicht first introduced
fast-switching high-vin converters.
To overcome the losses, speed, and
substrate coupling noise challenges
associated with fast switching, soft-/
zero-voltage switching and a parallel
resonant converter were proposed.
Wicht offered design examples,
including on the topics of automotive,
wearables, and gallium nitride.
In the second part of his lecture,
Wicht addressed the design of integrated
dc-dc (direct connect)
converters. As power management
system behavior and performance
strongly depend on
circuit-level implementation, the
second part of the talk was dedicated
to the design of dc-dc converter
building blocks like power
switches and gate drivers and their
supply, level shifters, and error
amplifiers as well as control loop
and current-sensing techniques.
The second virtual Distinguished
Lecturer seminar took place on
19 May 2021. Dr. Alvin Loke from NXP
Semiconductors gave the talk " Nanoscale
FinFET Technology for Circuit
Designers. " Loke began his
lecture with a brief history of transistor
evolution to motivate the migration
from planar to the fully depleted
FinFET. CMOS scaling maintains economic
relevance, with monolithic
5-nm systems on chip recently released
into the consumer marketplace
and 3 nm in the early stages of
product development. The modest
feature-size reduction and design/
technology innovations
that are co-optimized for
logic and static randomaccess
memory scaling
continue to offer compelling
node-to-node power,
performance, area, and
cost benefits. Loke summarized
the key process
technology elements
that have enabled the
continued the lively discussion
with Loke.
For the noise
simulations,
he presented
concatenated
simulations at the
chip and system
levels.
FinFET CMOS nodes, highlighting the
resulting device technology characteristics
and the ensuing impact of
the challenges, such as more significant
parasitics and layout-dependent
effects, on design.
To address the growing effort required
for physical design closure,
Loke covered design strategies, including
both density-friendly and
continuous active-area layouts,
and template-based analog cells.
He concluded with a discussion of
what remains in FinFET development
and a peek at the transistor
architectures on the horizon. During
the Q&A session, the audience
On 25 May, Prof. Makoto Nagata
from Kobe University gave the online
seminar " RF Noise Coupling-Understanding,
Mitigation and Impacts
on Wireless Communication Performance. "
First, Nagata introduced
the interference caused
by switching circuits
in wireless communication
systems and
studied the onboard
electromagnetic
noise
measurements and onchip
voltage noise measurements.
For the noise
simulations, he presented
concatenated simulations
at the chip and system levels.
By using chip-package-system boardcombined
circuit models, substrate
coupling noise can be simulated, and
a test chip with an on-chip noise generator
and monitor was measured to
verify the full-chip simulation. Loke
talked about the wireless system-level
simulation utilized to evaluate the impacts
of coupled RF noise on wireless
performance using throughput metrics.
He concluded his presentation by
recommending three-terminal capacitors
for onboard noise reduction and
provided evaluation examples.
-Milin Zhang, Le Ye, and Liyuan Liu
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2021
49
IEEE Solid-States Circuits Magazine - Summer 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2021
