IEEE Solid-States Circuits Magazine - Summer 2021 - 56

Prof. Nagata introduces his lecture and key concept.
highlighted the importance of multilevel
noise analyses increase from the
viewpoint of highly heterogeneous
integration. Additionally, an extensive
presentation of the concept of on-chip
noise monitoring (OCM) [2] demonstrated
the methods that are utilized
to take on-chip power-noise measurements
using these characteristics.
An in-place diagnosis uses OCM,
which sheds light on in-package
problems. It enables the exploration
of on-chip SI/PI diagnostic features
within advanced packaging structures,
that is, 2D (face down), 2.5D
(fan out), and even 3D (stacked).
This made for a nice transition to
3D IC packaging. The essential takeaway
from this discussion is that 3D
IC packaging provides potential advantages
[3], including that densely
integrated 3D power grids with distributed
through-silicon vias are advantageous
from the standpoint of
EMC and ESD [4].
Prof. Nagata shares the measured and simulated results.
Following the presentation was a
detailed Q&A session on the modeling
aspects of PI and SI, concluding
with the advantages of 3D IC packaging
from an ESD standpoint. The participant
feedback was very positive
and expressed an appreciation for
the breadth and depth of this infrequently
addressed topic.
-Mathieu Coustans,
Makoto Nagata, Michel Bron,
Domenico Pepe, and Taekwang Jang
References
[1] " IEEE Swiss SSC distinguished lecture
(webinar):
IC chip and packaging interactions
in design for SI, PI, EMC and ESD. "
IEEE vTools. https://events.vtools.ieee
.org/m/267365
[2] M. Nagata, J. Nagai, T. Morie, and A. Iwata,
" Measurements and analyses of substrate
noise waveform in mixed signal
IC environment, " IEEE Trans. Comput.Aided
Design Integr. Circuits Syst., vol.
19, no. 6, pp. 671-678, June 2000. doi:
10.1109/43.848088.
The Q&A session with Prof. Nagata and attendees.
on noise simulation and diagnostic
techniques and the second on power
noise problems and solutions in
advanced packaging.
Chip-package-system board power
noise simulation includes packagingcircuit
interaction for SI, PI, EMC,
and ESD characteristics. This section
[3] S. Takaya et al., " A 100GB/s wide I/O with
4096b TSVs through an active silicon interposer
with in-place waveform capturing, "
in Proc. IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, 2013, pp. 434-
435. doi: 10.1109/ISSCC.2013.6487803.
[4] M. Nagata et al., " CDM protection of a 3D
TSV memory IC with a 100 GB/s Wide I/O
data bus, " in Proc. EOS/ESD Symp., Sept.
2014, pp. 1-7.
56 SUMMER 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
https://events.vtools.ieee.org/m/267365 https://events.vtools.ieee.org/m/267365

IEEE Solid-States Circuits Magazine - Summer 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2021

Contents
IEEE Solid-States Circuits Magazine - Summer 2021 - Cover1
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